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64/128 Channel picoTDC unit for FERS-5200

A5203

Home Modular Pulse Processing ElectronicsRead Out SystemsFERS-5200 Boards A5203

FERS-5200 is a frontโ€end readout system designed for the readout of large detector arrays, such as SiPMs, multiโ€anode PMTs, Silicon Strip detectors, Wire Chambers, GEMs, Gas Tubes and others. FERSโ€5200 is a distributed and scalable system, where each unit is a small card that houses 64 or 128 channels. It features a detector specific Front-End interfaced to a common infrastructure that guarantees readout interfaces, slow control and synchronization. Typically, the front-end is based on ASIC chips that allow for high density, cost effective integration of multi-channel readout electronics into small size and low power modules. FERS is a flexible platform: combining the same back-end (i.e. readout architecture and interface) with different types of front-end to fit a wide range of detectors.

The A5203 (and DT5203, which is the boxed version for desktop use), part of the FERS-5200 family, is a Time-to-Digital Converter for high-resolution multi-hit time measurements that bases its functionality on the picoTDC chip (produced by CERN). The A5203B houses an additional mezzanine card with a second picoTDC chip, thus implementing a 128 channel TDC module.

Each readout channel accepts LVDS signals and measures the time stamp of both rising and falling edges with an LSB of 3.125 ps. In this way, the unit is able to reconstruct Time of Arrival (ToA) of signals as an absolute timestamp or as a ฮ”T with respect to a common Tref pulse. The picoTDC can also acquire Time over Threshold (ToT) information and combine it with the edge time stamp. The ToT allows for amplitude estimation, energy spectrum reconstruction, and timing walk correction. The latter permits to achieve optimal timing resolution with no need of Constant Fraction Discriminators.

The A5203 supports Common Start, Common Stop, Trigger Matching and Streaming acquisition modes. Have a look at FAQ for more details.

For small setups a single A5203 unit can be used stand alone, without any additional hardware, by simply connecting the unit to a PC via USB 2.0 or Ethernet 10/100T. For large readout systems, a flexible and scalable network of units can be created by means of the high speed optical link called TDlink that allows up to 16 FERSโ€5200 units to be connected in daisy chain (ring) providing data readout, synchronization between the units and broadcasting of commands (e.g. triggers, time resets, etc.). The DT5215 is a data collector board (FERSโ€CB) housing 8 TDlink masters that will make it possible to manage up to 128 FERSโ€5200 units.

The A5203 is fully supported by the CAEN Janus 5203 Open Source software on Windowsยฎ and Linuxยฎ. Janus can run in console mode (C program, without graphics) or connected to a GUI written in Python. The GUI has configuration and run control panels that simplify the data acquisition management. Both console and GUI modes permits to acquire data from multiple boards, manage the event building and timing histograms (ToA and/or ToT), display data statistics (hit rate, throughput, etcโ€ฆ), plot histograms, and save output, including spectra and list files with the acquired timing data.

In addition, the A5203 is supported by the following third-party software:

  • MIDAS_TRIUMF_DAQ

A wide range of adapters and cables has been also specifically designed for FERS-5200 boards, in order to provide versatility of choice and the ability to remotely operate the detectors, a complete list is available here.


Features

  • 64/128-ch TDC unit for high-resolution timing applications housing the CERN picoTDC

  • Part of FERS-5200, the CAEN platform for the readout of large arrays of detectors (SiPM, MA-PMTs, Gas Tubes, Si detectors, โ€ฆ)

  • Timing resolution: LSB = 3.125 ps, RMS typ. โˆผ 7 ps

  • TDC dynamic range: up to 26 bit (โˆผ 210 ฮผs). Extendable to 56 bit in the FPGA

  • Inputs: differential LVDS signals (max common mode = 1.2 V; max absolute voltage = 1.45 V). NIM, TTL or analog signals through dedicated adapters.

  • Acquisition of leading/trailing edge Time of Arrival (ToA), or leading edge ToA plus Time over Threshold (ToT) of the input signals

  • Scalability and easy-synch: up to 128 cards (8192/16384 channels) can be managed and synchronized by a single DT5215 Concentrator Board, thanks to the optical TDlink

  • Janus 5203 open source software available for board configuration and DAQ control

  • Flexibility: a full range of accessories for different kind of applications

  • Boxed FERS unit (DT5203) for desktop use available โ€“ 64 channels only

Accessories

A5260

Remotization cable for FERS-5200 boards

A5255

17x2 pin 2.54 mm pitch Quad Connector Adapter for A5203/DT5203

A5270

FERS cooling fan

A5256

16+1 Channels Discriminator for A5203/DT5203

Ordering Options

Code Description
WA5203BXAAAA

A5203B – 128 Channel pico-TDC unit for FERS-5200

 

(In production)

RoHS
WA5203XAAAAA

A5203 – 64 Channel pico-TDC unit for FERS-5200

 

(In production)

RoHS
Data Sheet Manual Download Compare

A5203: Data Sheets

Name
Revision
Format
File Size
Last Update
A52xx - Accessories for A5203 FERS-5200 Units
2
pdf
2.42 Mb
01/10/2024
A5203/DT5203 - 64/128 Channel picoTDC unit for FERS-5200
2
pdf
2.03 Mb
14/10/2025

A5203: Manuals

Name
Revision
Format
File Size
Last Update
UM9636 - Janus 5203 Software User Manual
0
pdf
4.96 Mb
07/02/2024
UM9085 - A5203/DT5203 User Manual
0
pdf
16.46 Mb
18/10/2023

A5203: Download

Presentations

Name
Revision
Format
File Size
Last Update
Poster IEEE: Characterization of A Compact TDC Unit With Picosecond Timing Capabilities
0
pdf
5.38 Mb
10/02/2025

Brochures / Flyers

Name
Revision
Format
File Size
Last Update
FERS5200 - Front-End Readout System
0
pdf
9.75 Mb
10/09/2025

Driver

Name
Revision
Format
File Size
Last Update
OS
FERS USB Driver Windows 10 (64-bit)
1.0.0.4
zip
4.81 Mb
27/04/2021
Windows

Applications SW

Name
Revision
Format
File Size
Last Update
OS
Janus 5203 - CAEN A5203(B)/DT5203 Readout Software
3.0.0
zip
46.46 Mb
29/05/2025
Windows
Janus 5203 - CAEN A5203(B)/DT5203 Readout Software
3.0.0
gz
5.2 Mb
29/05/2025
Linux
Name
Revision
Format
File Size
Last Update
A5203(B)/DT5203 FPGA Firmware
4
ffu
2.54 Mb
10/03/2025
Microcontroller Firmware
3
zip
25.16 Mb
17/06/2025

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