| CAEN FERS Library v1.1.4 SDK for FERS systems

FERS_Registers_5215.h
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1
17#ifndef _REGISTERS_5215_H
18#define _REGISTERS_5215_H // Protect against multiple inclusion
19
20// *****************************************************************
21// Virtual Registers of the concentrator
22// *****************************************************************
23// Register virtual address map
24#define VR_IO_STANDARD 0 // IO standard (NIM or TTL). Applies to all I/Os
25#define VR_IO_FA_DIR 1 // Direction of FA
26#define VR_IO_FB_DIR 2
27#define VR_IO_RA_DIR 3
28#define VR_IO_RB_DIR 4
29#define VR_IO_FA_FN 5 // Function of FA when used as output
30#define VR_IO_FB_FN 6
31#define VR_IO_RA_FN 7
32#define VR_IO_RB_FN 8
33#define VR_IO_FOUT_FN 9 // Funtion of the eigth F_OUT
34#define VR_IO_VETO_FN 10 // Veto source
35#define VR_IO_FIN_MASK 11 // F_IN enable mask
36#define VR_IO_FOUT_MASK 12 // F_OUT enable mask
37#define VR_IO_REG_VALUE 13 // Register controlled I/O
38#define VR_IO_TP_PERIOD 14 // Internal Test Pulse period
39#define VR_IO_TP_WIDTH 15 // Internal Test Pulse width
40#define VR_IO_CLK_SOURCE 16 // Clock source
41#define VR_IO_SYNC_OUT_A_FN 17 // Function of SYNC_OUT (RJ45)
42#define VR_IO_SYNC_OUT_B_FN 18
43#define VR_IO_SYNC_OUT_C_FN 19
44#define VR_IO_MASTER_SALVE 20 // Board is master or slave
45#define VR_IO_SYNC_PULSE_WIDTH 21 // Sync pulse width
46#define VR_IO_SYNC_SEND 22 // Send a sync pulse
47#define VR_SYNC_DELAY 23 // node to node delay in the daisy chain (used to fine tune the sync skew)
48#define VR_FIN_MAJORITY 24
49#define VR_IO_PPS_SOURCE 25
50#define VR_IO_PLL_STATUS 26
51#define VR_IO_LED_TEST_1 27
52#define VR_IO_LED_TEST_2 28
53#define VR_DMA_FLAGS_INFO 29 // Almost Full level of the INFO buffer (event descriptor table)
54#define VR_DMA_FLAGS_DATA 30 // Almost Full level of the DATA buffer (event payload)
55#define VR_ENABLED_LINKS 31 // Enable mask of the optical links
56#define VR_IO_DEBUG 32 // Digital Probes (allows some internal signals to be routed to the FA/FB outputs)
57
58
59// Register values
60#define VR_IO_SYNCSOURCE_ZERO 0
61#define VR_IO_SYNCSOURCE_SW_PULSE 1
62#define VR_IO_SYNCSOURCE_SW_REG 2
63#define VR_IO_SYNCSOURCE_FA 3
64#define VR_IO_SYNCSOURCE_FB 4
65#define VR_IO_SYNCSOURCE_RA 5
66#define VR_IO_SYNCSOURCE_RB 6
67#define VR_IO_SYNCSOURCE_GPS_PPS 7
68#define VR_IO_SYNCSOURCE_CLK_REF 8
69
70#define VR_IO_BOARD_MODE_MASTER 0
71#define VR_IO_BOARD_MODE_SLAVE 1
72
73#define VR_IO_STANDARD_IO_NIM 0
74#define VR_IO_STANDARD_IO_TLL 1
75
76#define VR_IO_DIRECTION_OUT 0
77#define VR_IO_DIRECTION_IN_R50 1
78#define VR_IO_DIRECTION_IN_HIZ 2
79
80#define VR_IO_FUNCTION_REGISTER 0
81#define VR_IO_FUNCTION_LOGIC_OR 1
82#define VR_IO_FUNCTION_LOGIC_AND 2
83#define VR_IO_FUNCTION_MAJORITY 3
84#define VR_IO_FUNCTION_TEST_PULSE 4
85#define VR_IO_FUNCTION_SYNC 5
86#define VR_IO_FUNCTION_FA_IN 6
87#define VR_IO_FUNCTION_FB_IN 7
88#define VR_IO_FUNCTION_RA_IN 8
89#define VR_IO_FUNCTION_RB_IN 9
90#define VR_IO_FUNCTION_ZERO 15
91
92#define VR_IO_CLKSOURCE_INTERNAL 0
93#define VR_IO_CLKSOURCE_LEMO 1
94#define VR_IO_CLKSOURCE_SYNC 2
95#define VR_IO_CLKSOURCE_RA 3
96
97// Digital Probes (for debug)
98#define VR_DPROBE_MON_TX_SYNC_SHORT 0x01
99#define VR_DPROBE_MON_TX_SYNC_ALIGN 0x02
100#define VR_DPROBE_MON_TX_SYNC_LONG 0x03
101#define VR_DPROBE_MON_TX_TIMING_SEND 0x04
102#define VR_DPROBE_MON_TX_NORMAL_SEND 0x05
103#define VR_DPROBE_MON_TX_TLAST_SEND 0x06
104#define VR_DPROBE_MON_TX_DATA_SEND 0x07
105#define VR_DPROBE_MON_TX_SYNC_PENDING 0x08
106#define VR_DPROBE_MON_TX_FIFOFULL 0x09
107#define VR_DPROBE_MON_TX_TVALID 0x0A
108#define VR_DPROBE_MON_TX_TREADY 0x0B
109#define VR_DPROBE_SC_BUSY 0x10
110#define VR_DPROBE_SC_DATA_WR 0x11
111#define VR_DPROBE_SC_INT_RD 0x12
112#define VR_DPROBE_SC_INT_WR 0x13
113#define VR_DPROBE_SC_COMMIT 0x14
114#define VR_DPROBE_SC_ACK 0x15
115#define VR_DPROBE_SC_NACK 0x16
116#define VR_DPROBE_STR_SOP 0x17
117#define VR_DPROBE_STR_EOP 0x18
118#define VR_DPROBE_STR_EOB 0x19
119#define VR_DPROBE_STR_DATA_VALID 0x20
120#define VR_DPROBE_CMD_BUSY 0x21
121#define VR_DPROBE_CMD_COMMIT 0x22
122#define VR_DPROBE_ENUMERATEBOARD 0x23
123#define VR_DPROBE_ENUMERATION_COMPLETED 0x24
124#define VR_DPROBE_SEND_T0 0x25
125#define VR_DPROBE_G_REINIT_LINK 0x26
126#define VR_DPROBE_READOUT_READY 0x27
127#define VR_DPROBE_MON_AXSM_WRITEREG 0x30
128#define VR_DPROBE_MON_AXSM_READREG 0x31
129#define VR_DPROBE_MON_AXSM_SENDCMD 0x32
130#define VR_DPROBE_MON_AXSM_SENDTOKEN 0x33
131#define VR_DPROBE_MON_AXSM_PENDING_TOKEN 0x34
132#define VR_DPROBE_MON_AXSM_PENDING_REG 0x35
133
134// TDlink error codes and status bits
135#define CNC_STATUS_INVALID_CHAIN 1
136#define CNC_STATUS_INVALID_BOARD 2
137#define CNC_STATUS_INVALID_FIRMWARE 3
138#define CNC_STATUS_CHAIN_NOT_INITIALIZED 4
139#define CNC_STATUS_UNABLE_TO_MAP_MEMORY_TO_USER_SPACE 5
140#define CNC_STATUS_UNABLE_TO_OPEN_DEV_MEM 6
141#define CNC_STATUS_UNABLE_TO_ALLOCATE_USER_MEMORY 7
142#define CNC_STATUS_UANBLE_TO_ALLOCATE_KERNEL_MEMORY 8
143#define CNC_STATUS_MEMORY_NOT_MAPPED 9
144#define CNC_STATUS_ADDRESS_OUT_OF_MEMORY 10
145#define CNC_STATUS_NO_MORE_SPACE 11
146#define CNC_STATUS_EMPTY 12
147#define CNC_STATUS_FULL 13
148#define CNC_STATUS_INVALID_SETTINGS 14
149#define CNC_STATUS_NO_MORE_SPACE_IN_THE_LIST 15
150#define CNC_STATUS_LIST_ALMOST_FULL 16
151#define CNC_STATUS_DMA_FAILED 17
152#define CNC_STATUS_CHAIN_DOWN 18
153#define CNC_STATUS_INVALID_IO_MODE 19
154#define CNC_STATUS_FPGA_IO_ERROR 20
155#define CNC_STATUS_IIC_IO_ERROR 21
156#define CNC_STATUS_INVALID_REGISTER 22
157#define CNC_STATUS_LINK_ERROR 23
158#define CNC_STATUS_UNABLE_TO_SET_LINK_PROP_DELAY 24
159#define CNC_STATUS_CHAIN_DISABLED 25
160#define CNC_STATUS_TIMEOUT 26
161#define CNC_STATUS_SFP_LOS 28
162#define CNC_STATUS_SFP_FAULT 29
163
164#endif