| CAEN FERS Library v1.1.4 SDK for FERS systems

FERS_Registers_520X.h
Go to the documentation of this file.
1
17#ifndef _REGISTERS_H
18#define _REGISTERS_H // Protect against multiple inclusion
19
20
21// ############################################################################################
22// FPGA REGISTERS
23// ############################################################################################
24
25
26// *****************************************************************
27// Individual Channel and Broadcast address converter
28// *****************************************************************
29#define INDIV_ADDR(addr, ch) (0x02000000 | ((addr) & 0xFFFF) | ((ch)<<16))
30#define BCAST_ADDR(addr) (0x03000000 | ((addr) & 0xFFFF))
31
37// *****************************************************************
38// FPGA Register Address Map common
39// *****************************************************************
40#define a_acq_ctrl 0x01000000
41#define a_run_mask 0x01000004
42#define a_trg_mask 0x01000008
43#define a_tref_mask 0x0100000C
44#define a_t0_out_mask 0x01000014
45#define a_t1_out_mask 0x01000018
46#define a_veto_mask 0x0100001C
47#define a_tref_delay 0x01000048
48#define a_tref_window 0x0100004C
49#define a_dwell_time 0x01000050
50#define a_list_size 0x01000054
51#define a_pck_maxcnt 0x01000064
52#define a_channel_mask_0 0x01000100
53#define a_channel_mask_1 0x01000104
54#define a_fw_rev 0x01000300
55#define a_acq_status 0x01000304
56#define a_real_time 0x01000308
57#define a_dead_time 0x01000310
58#define a_fpga_temp 0x01000348
59#define a_pid 0x01000400
60#define a_pcb_rev 0x01000404
61#define a_fers_code 0x01000408
62#define a_rebootfpga 0x0100FFF0
63#define a_test_led 0x01000228
64#define a_tdc_mode 0x0100022C
65#define a_tdc_data 0x01000230
66
67#define a_sw_compatib 0x01004000
68#define a_commands 0x01008000
69
70// *****************************************************************
71// FPGA Register Address Map 5202 Only
72// *****************************************************************
73#define a_validation_mask 0x01000010
74#define a_acq_ctrl2 0x01000020
75#define a_dprobe_5202 0x01000068
76#define a_citiroc_cfg 0x01000108
77#define a_citiroc_en 0x0100010C
78#define a_citiroc_probe 0x01000110
79#define a_qd_coarse_thr 0x01000114
80#define a_td_coarse_thr 0x01000118
81#define a_lg_sh_time 0x0100011C
82#define a_hg_sh_time 0x01000120
83#define a_hold_delay 0x01000124
84#define a_amux_seq_ctrl 0x01000128
85#define a_wave_length 0x0100012C
86#define a_scbs_ctrl 0x01000130
87#define a_scbs_data 0x01000134
88#define a_qdiscr_mask_0 0x01000138
89#define a_qdiscr_mask_1 0x0100013C
90#define a_tdiscr_mask_0 0x01000140
91#define a_tdiscr_mask_1 0x01000144
92#define a_tpulse_ctrl 0x01000200
93#define a_tpulse_dac 0x01000204
94#define a_hv_regaddr 0x01000210
95#define a_hv_regdata 0x01000214
96#define a_trgho 0x01000218
97#define a_dc_offset 0x01000220
98#define a_spi_data 0x01000224
99#define a_test_led 0x01000228
100#define a_tdc_mode 0x0100022C
101#define a_tdc_data 0x01000230
102#define a_tlogic_def 0x01000234
103#define a_tlogic_width 0x0100023C
104#define a_hit_width 0x01000238
105#define a_i2c_addr_5202 0x01000240
106#define a_i2c_data_5202 0x01000244
107#define a_t_or_cnt 0x01000350
108#define a_q_or_cnt 0x01000354
109#define a_hv_Vmon 0x01000356
110#define a_hv_Imon 0x01000358
111#define a_hv_status 0x01000360
112#define a_uC_status 0x01000600
113#define a_uC_shutdown 0x01000604
114#define a_zs_lgthr 0x02000000
115#define a_zs_hgthr 0x02000004
116#define a_qd_fine_thr 0x02000008
117#define a_td_fine_thr 0x0200000C
118#define a_lg_gain 0x02000010
119#define a_hg_gain 0x02000014
120#define a_hv_adj 0x02000018
121#define a_hitcnt 0x02000800
122
123// *****************************************************************
124// FPGA Register Address Map 5203 Only
125// *****************************************************************
126#define a_io_ctrl 0x01000020
127#define a_trg_delay 0x01000060
128#define a_dprobe_5203 0x01000110
129#define a_lsof_almfull_bsy 0x01000068
130#define a_lsof_almfull_skp 0x0100006C
131#define a_trgf_almfull 0x01000070
132#define a_tot_rej_lthr 0x01000074
133#define a_tot_rej_hthr 0x01000078
134#define a_trg_hold_off 0x0100007A
135#define a_strm_ptrg 0x0100007C
136#define a_i2c_addr_5203 0x01000200
137#define a_i2c_data_5203 0x01000204
138#define a_trg_cnt 0x01000318
139#define a_tdcro_status 0x0100031A
140#define a_rej_trg_cnt 0x0100031C
141#define a_zs_trg_cnt 0x01000320
142#define a_clk_out_phase 0x01000330
143#define a_board_temp 0x01000350
144#define a_tdc0_temp 0x01000354
145#define a_tdc1_temp 0x01000358
146#define a_spi_data 0x01000224
147
148// *****************************************************************
149// FPGA Register Address Map 5204 Only
150// *****************************************************************
151#define a_tlogic_mask_0 0x01000140
152#define a_tlogic_mask_1 0x01000144
153
156// *****************************************************************
157// FPGA Register Bit Fields
158// *****************************************************************
159// Status Register
160#define STATUS_READY (1 << 0)
161#define STATUS_FAIL (1 << 1)
162#define STATUS_RUNNING (1 << 2)
163#define STATUS_TDL_SYNC (1 << 3)
164#define STATUS_FPGA_OVERTEMP (1 << 4)
165#define STATUS_TDC_RO_ERR (1 << 5)
166#define STATUS_TDLINK_LOL (1 << 6)
167#define STATUS_TDC0_LOL (1 << 7)
168#define STATUS_TDC1_LOL (1 << 8)
169#define STATUS_RO_CLK_LOL (1 << 9)
170#define STATUS_TDL_DISABLED (1 << 10)
171#define STATUS_TDC0_OVERTEMP (1 << 11)
172#define STATUS_TDC1_OVERTEMP (1 << 12)
173#define STATUS_BOARD_OVERTEMP (1 << 13)
174#define STATUS_CRC_ERROR (1 << 14)
175#define STATUS_UNUSED_15 (1 << 15)
176#define STATUS_SPI_BUSY (1 << 16)
177#define STATUS_I2C_BUSY (1 << 17)
178#define STATUS_I2C_FAIL (1 << 18)
179
180
181// *****************************************************************
182// FPGA Commands
183// *****************************************************************
184#define CMD_TIME_RESET 0x11
185#define CMD_ACQ_START 0x12
186#define CMD_ACQ_STOP 0x13
187#define CMD_TRG 0x14
188#define CMD_RESET 0x15
189#define CMD_TPULSE 0x16
190#define CMD_RES_PTRG 0x17
191#define CMD_CLEAR 0x18
192#define CMD_VALIDATION 0x19
193#define CMD_SET_VETO 0x1A
194#define CMD_CLEAR_VETO 0x1B
195#define CMD_TDL_SYNC 0x1C
196#define CMD_USE_ICLK 0x1E
197#define CMD_USE_ECLK 0x1F
198#define CMD_CFG_ASIC 0x20
199
200
201// ############################################################################################
202// CITIROC REGISTERS
203// ############################################################################################
204
205#define crcfg_qdiscr_latch 0
206#define crcfg_sca_bias 1
207#define crcfg_pdet_mode_hg 2
208#define crcfg_pdet_mode_lg 3
209#define crcfg_ps_ctrl_logic 4
210#define crcfg_ps_trg_source 5
211#define crcfg_lg_pa_bias 6
212#define crcfg_pa_fast_sh 7
213#define crcfg_8bit_dac_ref 8
214#define crcfg_ota_bias 9
215#define crcfg_trg_polarity 10
216#define crcfg_enable_chtrg 11
217#define crcfg_enable_gtrg 16
218#define crcfg_enable_veto 17
219#define crcfg_repeat_raz 18
220
221#define SHAPING_TIME_12_5NS 6
222#define SHAPING_TIME_25NS 5
223#define SHAPING_TIME_37_5NS 4
224#define SHAPING_TIME_50NS 3
225#define SHAPING_TIME_62_5NS 2
226#define SHAPING_TIME_75NS 1
227#define SHAPING_TIME_87_5NS 0
228
229#define TEST_PULSE_SOURCE_EXT 0
230#define TEST_PULSE_SOURCE_T0_IN 1
231#define TEST_PULSE_SOURCE_T1_IN 2
232#define TEST_PULSE_SOURCE_PTRG 3
233#define TEST_PULSE_SOURCE_SW_CMD 4
234
235#define TEST_PULSE_PREAMP_LG 1
236#define TEST_PULSE_PREAMP_HG 2
237#define TEST_PULSE_PREAMP_BOTH 3
238
239#define TEST_PULSE_DEST_ALL -1
240#define TEST_PULSE_DEST_EVEN -2
241#define TEST_PULSE_DEST_ODD -3
242#define TEST_PULSE_DEST_NONE -4
243
244#define DPROBE_OFF 0
245#define DPROBE_PEAK_LG 1
246#define DPROBE_PEAK_HG 2
247#define DPROBE_HOLD 3
248#define DPROBE_START_CONV 4
249#define DPROBE_DATA_COMMIT 5
250#define DPROBE_DATA_VALID 6
251#define DPROBE_CLK_1024 7
252#define DPROBE_VAL_WINDOW 8
253#define DPROBE_T_OR 9
254#define DPROBE_Q_OR 10
255#define DPROBE_XROC_TRG 11
256
257#define GAIN_SEL_AUTO 0
258#define GAIN_SEL_HIGH 1
259#define GAIN_SEL_LOW 2
260#define GAIN_SEL_BOTH 3
261
262#define FAST_SHAPER_INPUT_HGPA 0
263#define FAST_SHAPER_INPUT_LGPA 1
264
265
266
267
268// ############################################################################################
269// RADIOROC REGISTERS
270// ############################################################################################
271
272// *****************************************************************
273// XROC register map
274// *****************************************************************
275#define a_XR_ChControl(i) (0x0000 + (63-i))
276#define a_XR_ASIC_bias 0x0040
277#define a_XR_common_cfg 0x0041
278#define a_XR_out_cfg 0x0042
279#define a_XR_event_val 0x0043
280
281// *****************************************************************
282// XROC reg data struct
283// *****************************************************************
284 typedef struct {
285 struct { // Addr - SubAddr
286 uint8_t r0_inDAC; // 0+CH - 0
287 uint8_t r1_pat_Gain_Comp; // 0+CH - 1
288 uint8_t r2_LG_HG_Gain; // 0+CH - 2
289 uint8_t r3_LG_HG_Tau; // 0+CH - 3
290 uint8_t r4_calibDacT1; // 0+CH - 4
291 uint8_t r5_calibDacT2; // 0+CH - 5
292 uint8_t r6_EnMask1; // 0+CH - 6
293 uint8_t r7_EnMask2; // 0+CH - 7
294 uint8_t r66_ProbeSwitchCmd; // 0+CH - 66
295 } ChControl[64];
296 struct { // Addr - SubAddr
297 uint8_t r0_inDAC0; // 64 - 0
298 uint8_t r1_inDAC1; // 64 - 1
299 uint8_t r2_calDAC_paT; // 64 - 2
300 uint8_t r3_pa_LG_HG; // 64 - 3
301 uint8_t r4_sh_HG; // 64 - 4
302 uint8_t r5_sh_LG; // 64 - 5
303 uint8_t r6_pdbuff_pdetect; // 64 - 6
304 uint8_t r7_FCNpdet_FCPpdet; // 64 - 7
305 uint8_t r8_FCNpbuf_FCPpbuf; // 64 - 8
306 uint8_t r9_dis1a; // 64 - 9
307 uint8_t r10_dis1b_dis2a; // 64 - 10
308 uint8_t r11_dis2b; // 64 - 11
309 uint8_t r12_dis_charge; // 64 - 12
310 uint8_t r13_EnMask1; // 64 - 13
311 uint8_t r14_EnMask2; // 64 - 14
312 } ASICBias;
313 struct { // Addr - SubAddr
314 uint8_t r0_BandGap; // 65 - 0
315 uint8_t r1_DAC1a; // 65 - 1
316 uint8_t r2_DAC1b_DAC2a; // 65 - 2
317 uint8_t r3_DAC2b_DACqa; // 65 - 3
318 uint8_t r4_DACqb; // 65 - 4
319 uint8_t r5_Ib_thrDac; // 65 - 5
320 uint8_t r6_Ib_thrDac; // 65 - 6
321 uint8_t r7_EnMask; // 65 - 7
322 uint8_t r8_delay; // 65 - 8
323 uint8_t r9_; // 65 - 9
324 uint8_t r10_; // 65 - 10
325 uint8_t r11_; // 65 - 11
326 uint8_t r12_; // 65 - 12
327 uint8_t r66_; // 65 - 66
328 } Common;
329 struct { // Addr - SubAddr
330 uint8_t r0_BandGap; // 65 - 0
331 uint8_t r1_DAC1a; // 65 - 1
332 uint8_t r2_DAC1b_DAC2a; // 65 - 2
333 uint8_t r3_DAC2b_DACqa; // 65 - 3
334 uint8_t r4_DACqb; // 65 - 4
335 uint8_t r5_Ib_thrDac; // 65 - 5
336 uint8_t r6_Ib_thrDac; // 65 - 6
337 uint8_t r7_EnMask; // 65 - 7
338 uint8_t r8_delay; // 65 - 8
339 uint8_t r9_; // 65 - 9
340 uint8_t r10_; // 65 - 10
341 uint8_t r11_; // 65 - 11
342 uint8_t r12_; // 65 - 12
343 uint8_t r66_; // 65 - 66
344 } Outing;
345
346} XR_Cfg_t;
347
348
349
350// ############################################################################################
351// PICOTDC REGISTERS
352// ############################################################################################
353
354// *****************************************************************
355// picoTDC register Map
356// *****************************************************************
357#define a_pTDC_Control 0x0004
358#define a_pTDC_Enable 0x0008
359#define a_pTDC_Header 0x000C
360#define a_pTDC_TrgWindow 0x0010
361#define a_pTDC_Trg0Del_ToT 0x0014
362#define a_pTDC_BunchCount 0x0018
363#define a_pTDC_EventID 0x001C
364#define a_pTDC_Ch_Control(i) (0x0020 + (i)*4)
365#define a_pTDC_Buffers 0x0120
366#define a_pTDC_Hit_RX_TX 0x0124
367#define a_pTDC_DLL_TG 0x0128
368#define a_pTDC_PLL1 0x0130
369#define a_pTDC_PLL2 0x0134
370#define a_pTDC_Clocks 0x0138 // R/W -
371#define a_pTDC_ClockShift 0x013C // R/W -
372#define a_pTDC_Hit_RXen_T 0x0140 // R/W -
373#define a_pTDC_Hit_RXen_B 0x0144 // R/W -
374#define a_pTDC_PulseGen1 0x0148 // R/W -
375#define a_pTDC_PulseGen2 0x014C // R/W -
376#define a_pTDC_PulseGen3 0x0150 // R/W -
377#define a_pTDC_ErrorFlagCtrl 0x0154 // R/W -
378#define a_pTDC_Ch_Status(i) (0x0160 + (i)*4) // R -
379#define a_pTDC_Trg_Status(i) (0x0260 + (i)*4) // R -
380#define a_pTDC_RO_Status(i) (0x0270 + (i)*4) // R -
381#define a_pTDC_Cfg_Parity(i) (0x0280 + (i)*4) // R -
382#define a_pTDC_PLL_Caps 0x28C // R -
383#define a_pTDC_DelayAdjust 0xFFFC // W -
384
385// *****************************************************************
386// picoTDC Data Structures
387// *****************************************************************
388
389 typedef struct {
390 // ------------------------------------------------ Control
391 union {
392 struct {
393 uint32_t magic_word : 8;
394 uint32_t digital_reset : 1;
395 uint32_t bunchcount_reset : 1;
396 uint32_t eventid_reset : 1;
397 uint32_t dropcnts_reset : 1;
398 uint32_t errorcnts_reset : 1;
399 uint32_t trigger_create : 1;
400 uint32_t trigger_create_single : 1;
401 uint32_t reserved1 : 17;
402 } bits;
403 uint32_t reg;
404 } Control;
405 // ------------------------------------------------ Enable
406 union {
407 struct {
408 uint32_t reserved1 : 1;
409 uint32_t falling_en : 1;
410 uint32_t single_readout_en : 1;
411 uint32_t reserved2 : 2;
412 uint32_t highres_en : 1;
413 uint32_t dig_rst_ext_en : 1;
414 uint32_t bx_rst_ext_en : 1;
415 uint32_t eid_rst_ext_en : 1;
416 uint32_t reserved3 : 8;
417 uint32_t crossing_en : 1;
418 uint32_t rx_en_extref : 1;
419 uint32_t rx_en_bxrst : 1;
420 uint32_t rx_en_eidrst : 1;
421 uint32_t rx_en_trigger : 1;
422 uint32_t rx_en_reset : 1;
423 uint32_t left_suppress : 1;
424 uint32_t channel_split2 : 1;
425 uint32_t channel_split4 : 1;
426 uint32_t reserved4 : 6;
427 } bits;
428 uint32_t reg;
429 } Enable;
430 // ------------------------------------------------ Header
431 union {
432 struct {
433 uint32_t untriggered : 1;
434 uint32_t reserved1 : 1;
435 uint32_t relative : 1;
436 uint32_t second_header : 1;
437 uint32_t full_events : 1;
438 uint32_t trigger_ch0_en : 1;
439 uint32_t reserved2 : 2;
440 uint32_t header_fields0 : 3;
441 uint32_t reserved3 : 1;
442 uint32_t header_fields1 : 3;
443 uint32_t reserved4 : 1;
444 uint32_t header_fields2 : 3;
445 uint32_t reserved5 : 1;
446 uint32_t header_fields3 : 3;
447 uint32_t reserved6 : 1;
448 uint32_t max_eventsize : 8;
449 } bits;
450 uint32_t reg;
451 } Header;
452 // ------------------------------------------------ TrgWindow
453 union {
454 struct {
455 uint32_t trigger_latency : 13;
456 uint32_t reserved1 : 3;
457 uint32_t trigger_window : 13;
458 uint32_t reserved2 : 3;
459 } bits;
460 uint32_t reg;
461 } TrgWindow;
462
463 // ------------------------------------------------ Trg0Del_ToT
464 union {
465 struct {
466 uint32_t trg_ch0_delay : 13;
467 uint32_t reserved1 : 3;
468 uint32_t tot : 1;
469 uint32_t tot_8bit : 1;
470 uint32_t tot_startbit : 5;
471 uint32_t tot_saturate : 1;
472 uint32_t tot_leadingstartbit : 4;
473 uint32_t reserved2 : 4;
474 } bits;
475 uint32_t reg;
476 } Trg0Del_ToT;
477 // ------------------------------------------------ BunchCount
478 union {
479 struct {
480 uint32_t bunchcount_overflow : 13;
481 uint32_t reserved1 : 3;
482 uint32_t bunchcount_offset : 13;
483 uint32_t reserved2 : 3;
484 } bits;
485 uint32_t reg;
486 } BunchCount;
487 // ------------------------------------------------ EventID
488 union {
489 struct {
490 uint32_t eventid_overflow : 13;
491 uint32_t reserved1 : 3;
492 uint32_t eventid_offset : 13;
493 uint32_t reserved2 : 3;
494 } bits;
495 uint32_t reg;
496 } EventID;
497 // ------------------------------------------------ Ch_Control[64]
498 union {
499 struct {
500 uint32_t channel_offset : 26;
501 uint32_t falling_en_tm : 1;
502 uint32_t highres_en_tm : 1;
503 uint32_t scan_en_tm : 1;
504 uint32_t scan_in_tm : 1;
505 uint32_t reserved1 : 1;
506 uint32_t channel_enable : 1;
507 } bits;
508 uint32_t reg;
509 } Ch_Control[64];
510 // ------------------------------------------------ Buffers
511 union {
512 struct {
513 uint32_t channel_buffer_size : 4;
514 uint32_t readout_buffer_size : 4;
515 uint32_t trigger_buffer_size : 4;
516 uint32_t disable_ro_reject : 1;
517 uint32_t errorcnts_saturate : 1;
518 uint32_t reserved1 : 2;
519 uint32_t max_grouphits : 8;
520 uint32_t reserved2 : 8;
521 } bits;
522 uint32_t reg;
523 } Buffers;
524 // ------------------------------------------------ Hit_RX_TX
525 union {
526 struct {
527 uint32_t hrx_top_delay : 4;
528 uint32_t hrx_top_bias : 4;
529 uint32_t hrx_top_filter_trailing : 1;
530 uint32_t hrx_top_filter_leading : 1;
531 uint32_t hrx_top_en_r : 1;
532 uint32_t hrx_top_en : 1;
533 uint32_t hrx_bot_delay : 4;
534 uint32_t hrx_bot_bias : 4;
535 uint32_t hrx_bot_filter_trailing : 1;
536 uint32_t hrx_bot_filter_leading : 1;
537 uint32_t hrx_bot_en_r : 1;
538 uint32_t hrx_bot_en : 1;
539 uint32_t tx_strenght : 2;
540 uint32_t reserved1 : 6;
541 } bits;
542 uint32_t reg;
543 } Hit_RX_TX;
544 // ------------------------------------------------ DLL_TG
545 union {
546 struct {
547 uint32_t dll_bias_val : 7;
548 uint32_t dll_bias_cal : 5;
549 uint32_t dll_cp_comp : 3;
550 uint32_t dll_ctrlval : 4;
551 uint32_t dll_fixctrl : 1;
552 uint32_t dll_extctrl : 1;
553 uint32_t dll_cp_comp_dir : 1;
554 uint32_t dll_en_bias_cal : 1;
555 uint32_t tg_bot_nen_fine : 1;
556 uint32_t tg_bot_nen_coarse : 1;
557 uint32_t tg_top_nen_fine : 1;
558 uint32_t tg_top_nen_coarse : 1;
559 uint32_t tg_cal_nrst : 1;
560 uint32_t tg_cal_parity_in : 1;
561 uint32_t reserved1 : 3;
562 } bits;
563 uint32_t reg;
564 } DLL_TG;
565 // ------------------------------------------------ PLL1
566 union {
567 struct {
568 uint32_t pll_cp_ce : 1;
569 uint32_t pll_cp_dacset : 7;
570 uint32_t pll_cp_irefcpset : 5;
571 uint32_t pll_cp_mmcomp : 3;
572 uint32_t pll_cp_mmdir : 1;
573 uint32_t pll_pfd_enspfd : 1;
574 uint32_t pll_resistor : 5;
575 uint32_t pll_sw_ext : 1;
576 uint32_t pll_vco_dacsel : 1;
577 uint32_t pll_vco_dacset : 7;
578 } bits;
579 uint32_t reg;
580 } PLL1;
581 // ------------------------------------------------ PLL2
582 union {
583 struct {
584 uint32_t pll_vco_dac_ce : 1;
585 uint32_t pll_vco_igen_start : 1;
586 uint32_t pll_railmode_vco : 1;
587 uint32_t pll_abuffdacset : 5;
588 uint32_t pll_buffce : 1;
589 uint32_t pll_afcvcal : 4;
590 uint32_t pll_afcstart : 1;
591 uint32_t pll_afcrst : 1;
592 uint32_t pll_afc_override : 1;
593 uint32_t pll_bt0 : 1;
594 uint32_t pll_afc_overrideval : 4;
595 uint32_t pll_afc_overridesig : 1;
596 uint32_t reserved1 : 10;
597 } bits;
598 uint32_t reg;
599 } PLL2;
600
601 // ------------------------------------------------ Clocks
602 union {
603 struct {
604 uint32_t hit_phase : 2;
605 uint32_t reserved1 : 2;
606 uint32_t trig_phase : 3;
607 uint32_t reserved2 : 1;
608 uint32_t bx_rst_phase : 3;
609 uint32_t reserved3 : 1;
610 uint32_t eid_rst_phase : 3;
611 uint32_t reserved4 : 1;
612 uint32_t par_speed : 2;
613 uint32_t reserved5 : 2;
614 uint32_t par_phase : 3;
615 uint32_t sync_clock : 1;
616 uint32_t ext_clk_dll : 1;
617 uint32_t reserved6 : 7;
618 } bits;
619 uint32_t reg;
620 } Clocks;
621 // ------------------------------------------------ ClockShift
622 union {
623 struct {
624 uint32_t reserved1 : 4;
625 uint32_t shift_clk1G28 : 4;
626 uint32_t shift_clk640M : 4;
627 uint32_t shift_clk320M : 4;
628 uint32_t shift_clk320M_ref : 4;
629 uint32_t shift_clk160M : 4;
630 uint32_t shift_clk80M : 4;
631 uint32_t shift_clk40M : 4;
632 } bits;
633 uint32_t reg;
634 } ClockShift;
635 // ------------------------------------------------ Hit_RXen_T
636 union {
637 struct {
638 uint32_t hrx_enable_t : 32;
639 } bits;
640 uint32_t reg;
641 } Hit_RXen_T;
642 // ------------------------------------------------ Hit_RXen_B
643 union {
644 struct {
645 uint32_t hrx_enable_b : 32;
646 } bits;
647 uint32_t reg;
648 } Hit_RXen_B;
649 // ------------------------------------------------ PulseGen1
650 union {
651 struct {
652 uint32_t pg_run : 1;
653 uint32_t pg_rep : 1;
654 uint32_t pg_direct : 1;
655 uint32_t pg_ini : 1;
656 uint32_t pg_en : 1;
657 uint32_t pg_strength : 2;
658 uint32_t reserved1 : 1;
659 uint32_t pg_rising : 18;
660 uint32_t reserved2 : 6;
661 } bits;
662 uint32_t reg;
663 } PulseGen1;
664 // ------------------------------------------------ PulseGen2
665 union {
666 struct {
667 uint32_t pg_phase : 8;
668 uint32_t pg_falling : 18;
669 uint32_t reserved1 : 6;
670 } bits;
671 uint32_t reg;
672 } PulseGen2;
673 // ------------------------------------------------ PulseGen3
674 union {
675 struct {
676 uint32_t pg_reload : 18;
677 uint32_t reserved2 : 14;
678 } bits;
679 uint32_t reg;
680 } PulseGen3;
681 // ------------------------------------------------ ErrorFlagCtrl
682 union {
683 struct {
684 uint32_t error_flags_1 : 10;
685 uint32_t error_flags_2 : 10;
686 uint32_t error_flags_3 : 10;
687 uint32_t reserved1 : 2;
688 } bits;
689 uint32_t reg;
690 } ErrorFlagCtrl;
691 // ------------------------------------------------ DelayAdjust
692 union {
693 struct {
694 uint32_t tg_delay_taps : 8;
695 uint32_t reserved1 : 24;
696 } bits;
697 uint32_t reg;
698 } DelayAdjust;
699
700 // ************************************************
701 // Status Regs (read only)
702 // ************************************************
703 // ------------------------------------------------ Ch_Status[64]
704 union {
705 struct {
706 uint32_t ch_fillgrade : 8;
707 uint32_t ch_dropped : 8;
708 uint32_t ch_parity : 4;
709 uint32_t scan_out : 1;
710 uint32_t reserved1 : 2;
711 uint32_t ch_stateerr : 1;
712 uint32_t reserved2 : 8;
713 } bits;
714 uint32_t reg;
715 } Ch_Status[64];
716 // ------------------------------------------------ Trg_Status[4]
717 union {
718 struct {
719 uint32_t tr_fillgrade : 8;
720 uint32_t tr_dropped : 8;
721 uint32_t tr_parity : 4;
722 uint32_t reserved1 : 3;
723 uint32_t tr_stateerr : 1;
724 uint32_t reserved2 : 8;
725
726 } bits;
727 uint32_t reg;
728 } Trg_Status[4];
729 // ------------------------------------------------ RO_Status[4]
730 union {
731 struct {
732 uint32_t ro_fillgrade : 8;
733 uint32_t ro_dropped : 8;
734 uint32_t ro_corrected : 4;
735 uint32_t reserved1 : 3;
736 uint32_t ro_multibiterr : 4;
737 uint32_t reserved2 : 5;
738
739 } bits;
740 uint32_t reg;
741 } RO_Status[4];
742 // ------------------------------------------------ Cfg_Parity[3]
743 union {
744 struct {
745 uint32_t parity : 32;
746 } bits;
747 uint32_t reg;
748 } Cfg_Parity[3];
749 // ------------------------------------------------ PLL_Caps
750 union {
751 struct {
752 uint32_t pll_selectedcap : 24;
753 uint32_t reserved1 : 8;
754 } bits;
755 uint32_t reg;
756 } PLL_Caps;
757
758} picoTDC_Cfg_t;
759
760
761// *****************************************************************
762// Address of I2C devices
763// *****************************************************************
764#define I2C_ADDR_TDC(i) (0x63 - (i))
765#define I2C_ADDR_PLL0 0x68
766#define I2C_ADDR_PLL1 0x69
767#define I2C_ADDR_PLL2 0x70
768#define I2C_ADDR_EEPROM_MEM 0x57
769#define I2C_ADDR_XR 0x78 // weeroc ASIC
770
771#endif
772
773
774
XR_Cfg_t
Definition: FERS_Registers_520X.h:284
XR_Cfg_t::r66_ProbeSwitchCmd
uint8_t r66_ProbeSwitchCmd
Definition: FERS_Registers_520X.h:294
XR_Cfg_t::r2_calDAC_paT
uint8_t r2_calDAC_paT
Definition: FERS_Registers_520X.h:299
XR_Cfg_t::r5_sh_LG
uint8_t r5_sh_LG
Definition: FERS_Registers_520X.h:302
XR_Cfg_t::r6_Ib_thrDac
uint8_t r6_Ib_thrDac
Definition: FERS_Registers_520X.h:320
XR_Cfg_t::r66_
uint8_t r66_
Definition: FERS_Registers_520X.h:327
XR_Cfg_t::r1_inDAC1
uint8_t r1_inDAC1
Definition: FERS_Registers_520X.h:298
XR_Cfg_t::r0_inDAC0
uint8_t r0_inDAC0
Definition: FERS_Registers_520X.h:297
XR_Cfg_t::r0_inDAC
uint8_t r0_inDAC
Definition: FERS_Registers_520X.h:286
XR_Cfg_t::r10_
uint8_t r10_
Definition: FERS_Registers_520X.h:324
XR_Cfg_t::r11_
uint8_t r11_
Definition: FERS_Registers_520X.h:325
XR_Cfg_t::r5_Ib_thrDac
uint8_t r5_Ib_thrDac
Definition: FERS_Registers_520X.h:319
XR_Cfg_t::r13_EnMask1
uint8_t r13_EnMask1
Definition: FERS_Registers_520X.h:310
XR_Cfg_t::r3_DAC2b_DACqa
uint8_t r3_DAC2b_DACqa
Definition: FERS_Registers_520X.h:317
XR_Cfg_t::r2_LG_HG_Gain
uint8_t r2_LG_HG_Gain
Definition: FERS_Registers_520X.h:288
XR_Cfg_t::r3_LG_HG_Tau
uint8_t r3_LG_HG_Tau
Definition: FERS_Registers_520X.h:289
XR_Cfg_t::r11_dis2b
uint8_t r11_dis2b
Definition: FERS_Registers_520X.h:308
XR_Cfg_t::r5_calibDacT2
uint8_t r5_calibDacT2
Definition: FERS_Registers_520X.h:291
XR_Cfg_t::r7_EnMask2
uint8_t r7_EnMask2
Definition: FERS_Registers_520X.h:293
XR_Cfg_t::r3_pa_LG_HG
uint8_t r3_pa_LG_HG
Definition: FERS_Registers_520X.h:300
XR_Cfg_t::r7_FCNpdet_FCPpdet
uint8_t r7_FCNpdet_FCPpdet
Definition: FERS_Registers_520X.h:304
XR_Cfg_t::r6_EnMask1
uint8_t r6_EnMask1
Definition: FERS_Registers_520X.h:292
XR_Cfg_t::r4_DACqb
uint8_t r4_DACqb
Definition: FERS_Registers_520X.h:318
XR_Cfg_t::r4_calibDacT1
uint8_t r4_calibDacT1
Definition: FERS_Registers_520X.h:290
XR_Cfg_t::r8_FCNpbuf_FCPpbuf
uint8_t r8_FCNpbuf_FCPpbuf
Definition: FERS_Registers_520X.h:305
XR_Cfg_t::r6_pdbuff_pdetect
uint8_t r6_pdbuff_pdetect
Definition: FERS_Registers_520X.h:303
XR_Cfg_t::r0_BandGap
uint8_t r0_BandGap
Definition: FERS_Registers_520X.h:314
XR_Cfg_t::r7_EnMask
uint8_t r7_EnMask
Definition: FERS_Registers_520X.h:321
XR_Cfg_t::r8_delay
uint8_t r8_delay
Definition: FERS_Registers_520X.h:322
XR_Cfg_t::r9_
uint8_t r9_
Definition: FERS_Registers_520X.h:323
XR_Cfg_t::r9_dis1a
uint8_t r9_dis1a
Definition: FERS_Registers_520X.h:306
XR_Cfg_t::r2_DAC1b_DAC2a
uint8_t r2_DAC1b_DAC2a
Definition: FERS_Registers_520X.h:316
XR_Cfg_t::r12_dis_charge
uint8_t r12_dis_charge
Definition: FERS_Registers_520X.h:309
XR_Cfg_t::r12_
uint8_t r12_
Definition: FERS_Registers_520X.h:326
XR_Cfg_t::r14_EnMask2
uint8_t r14_EnMask2
Definition: FERS_Registers_520X.h:311
XR_Cfg_t::r1_pat_Gain_Comp
uint8_t r1_pat_Gain_Comp
Definition: FERS_Registers_520X.h:287
XR_Cfg_t::r1_DAC1a
uint8_t r1_DAC1a
Definition: FERS_Registers_520X.h:315
XR_Cfg_t::r4_sh_HG
uint8_t r4_sh_HG
Definition: FERS_Registers_520X.h:301
XR_Cfg_t::r10_dis1b_dis2a
uint8_t r10_dis1b_dis2a
Definition: FERS_Registers_520X.h:307
picoTDC_Cfg_t
Definition: FERS_Registers_520X.h:389
picoTDC_Cfg_t::pll_vco_dacsel
uint32_t pll_vco_dacsel
Definition: FERS_Registers_520X.h:576
picoTDC_Cfg_t::falling_en_tm
uint32_t falling_en_tm
Definition: FERS_Registers_520X.h:501
picoTDC_Cfg_t::header_fields3
uint32_t header_fields3
Definition: FERS_Registers_520X.h:446
picoTDC_Cfg_t::shift_clk320M
uint32_t shift_clk320M
Definition: FERS_Registers_520X.h:627
picoTDC_Cfg_t::channel_split4
uint32_t channel_split4
Definition: FERS_Registers_520X.h:425
picoTDC_Cfg_t::pg_strength
uint32_t pg_strength
Definition: FERS_Registers_520X.h:657
picoTDC_Cfg_t::rx_en_eidrst
uint32_t rx_en_eidrst
Definition: FERS_Registers_520X.h:420
picoTDC_Cfg_t::highres_en
uint32_t highres_en
Definition: FERS_Registers_520X.h:412
picoTDC_Cfg_t::hrx_bot_delay
uint32_t hrx_bot_delay
Definition: FERS_Registers_520X.h:533
picoTDC_Cfg_t::pll_buffce
uint32_t pll_buffce
Definition: FERS_Registers_520X.h:588
picoTDC_Cfg_t::reserved5
uint32_t reserved5
Definition: FERS_Registers_520X.h:445
picoTDC_Cfg_t::second_header
uint32_t second_header
Definition: FERS_Registers_520X.h:436
picoTDC_Cfg_t::error_flags_1
uint32_t error_flags_1
Definition: FERS_Registers_520X.h:684
picoTDC_Cfg_t::bunchcount_offset
uint32_t bunchcount_offset
Definition: FERS_Registers_520X.h:482
picoTDC_Cfg_t::pg_phase
uint32_t pg_phase
Definition: FERS_Registers_520X.h:667
picoTDC_Cfg_t::hrx_top_en_r
uint32_t hrx_top_en_r
Definition: FERS_Registers_520X.h:531
picoTDC_Cfg_t::hrx_bot_en_r
uint32_t hrx_bot_en_r
Definition: FERS_Registers_520X.h:537
picoTDC_Cfg_t::pll_pfd_enspfd
uint32_t pll_pfd_enspfd
Definition: FERS_Registers_520X.h:573
picoTDC_Cfg_t::ro_fillgrade
uint32_t ro_fillgrade
Definition: FERS_Registers_520X.h:732
picoTDC_Cfg_t::reserved4
uint32_t reserved4
Definition: FERS_Registers_520X.h:426
picoTDC_Cfg_t::crossing_en
uint32_t crossing_en
Definition: FERS_Registers_520X.h:417
picoTDC_Cfg_t::shift_clk40M
uint32_t shift_clk40M
Definition: FERS_Registers_520X.h:631
picoTDC_Cfg_t::dll_cp_comp
uint32_t dll_cp_comp
Definition: FERS_Registers_520X.h:549
picoTDC_Cfg_t::full_events
uint32_t full_events
Definition: FERS_Registers_520X.h:437
picoTDC_Cfg_t::tot
uint32_t tot
Definition: FERS_Registers_520X.h:468
picoTDC_Cfg_t::tg_delay_taps
uint32_t tg_delay_taps
Definition: FERS_Registers_520X.h:694
picoTDC_Cfg_t::pll_vco_dac_ce
uint32_t pll_vco_dac_ce
Definition: FERS_Registers_520X.h:584
picoTDC_Cfg_t::rx_en_extref
uint32_t rx_en_extref
Definition: FERS_Registers_520X.h:418
picoTDC_Cfg_t::ro_dropped
uint32_t ro_dropped
Definition: FERS_Registers_520X.h:733
picoTDC_Cfg_t::tg_cal_nrst
uint32_t tg_cal_nrst
Definition: FERS_Registers_520X.h:559
picoTDC_Cfg_t::eid_rst_phase
uint32_t eid_rst_phase
Definition: FERS_Registers_520X.h:610
picoTDC_Cfg_t::highres_en_tm
uint32_t highres_en_tm
Definition: FERS_Registers_520X.h:502
picoTDC_Cfg_t::pll_bt0
uint32_t pll_bt0
Definition: FERS_Registers_520X.h:593
picoTDC_Cfg_t::trigger_latency
uint32_t trigger_latency
Definition: FERS_Registers_520X.h:455
picoTDC_Cfg_t::ro_corrected
uint32_t ro_corrected
Definition: FERS_Registers_520X.h:734
picoTDC_Cfg_t::left_suppress
uint32_t left_suppress
Definition: FERS_Registers_520X.h:423
picoTDC_Cfg_t::tot_leadingstartbit
uint32_t tot_leadingstartbit
Definition: FERS_Registers_520X.h:472
picoTDC_Cfg_t::max_grouphits
uint32_t max_grouphits
Definition: FERS_Registers_520X.h:519
picoTDC_Cfg_t::bx_rst_phase
uint32_t bx_rst_phase
Definition: FERS_Registers_520X.h:608
picoTDC_Cfg_t::error_flags_2
uint32_t error_flags_2
Definition: FERS_Registers_520X.h:685
picoTDC_Cfg_t::tr_fillgrade
uint32_t tr_fillgrade
Definition: FERS_Registers_520X.h:719
picoTDC_Cfg_t::reserved6
uint32_t reserved6
Definition: FERS_Registers_520X.h:447
picoTDC_Cfg_t::dll_cp_comp_dir
uint32_t dll_cp_comp_dir
Definition: FERS_Registers_520X.h:553
picoTDC_Cfg_t::bunchcount_reset
uint32_t bunchcount_reset
Definition: FERS_Registers_520X.h:395
picoTDC_Cfg_t::shift_clk640M
uint32_t shift_clk640M
Definition: FERS_Registers_520X.h:626
picoTDC_Cfg_t::trig_phase
uint32_t trig_phase
Definition: FERS_Registers_520X.h:606
picoTDC_Cfg_t::dll_en_bias_cal
uint32_t dll_en_bias_cal
Definition: FERS_Registers_520X.h:554
picoTDC_Cfg_t::shift_clk160M
uint32_t shift_clk160M
Definition: FERS_Registers_520X.h:629
picoTDC_Cfg_t::tg_cal_parity_in
uint32_t tg_cal_parity_in
Definition: FERS_Registers_520X.h:560
picoTDC_Cfg_t::channel_offset
uint32_t channel_offset
Definition: FERS_Registers_520X.h:500
picoTDC_Cfg_t::header_fields1
uint32_t header_fields1
Definition: FERS_Registers_520X.h:442
picoTDC_Cfg_t::ch_dropped
uint32_t ch_dropped
Definition: FERS_Registers_520X.h:707
picoTDC_Cfg_t::eventid_overflow
uint32_t eventid_overflow
Definition: FERS_Registers_520X.h:490
picoTDC_Cfg_t::tr_parity
uint32_t tr_parity
Definition: FERS_Registers_520X.h:721
picoTDC_Cfg_t::hrx_bot_bias
uint32_t hrx_bot_bias
Definition: FERS_Registers_520X.h:534
picoTDC_Cfg_t::errorcnts_saturate
uint32_t errorcnts_saturate
Definition: FERS_Registers_520X.h:517
picoTDC_Cfg_t::rx_en_reset
uint32_t rx_en_reset
Definition: FERS_Registers_520X.h:422
picoTDC_Cfg_t::hrx_bot_filter_leading
uint32_t hrx_bot_filter_leading
Definition: FERS_Registers_520X.h:536
picoTDC_Cfg_t::dll_extctrl
uint32_t dll_extctrl
Definition: FERS_Registers_520X.h:552
picoTDC_Cfg_t::tg_bot_nen_coarse
uint32_t tg_bot_nen_coarse
Definition: FERS_Registers_520X.h:556
picoTDC_Cfg_t::ch_stateerr
uint32_t ch_stateerr
Definition: FERS_Registers_520X.h:711
picoTDC_Cfg_t::pg_run
uint32_t pg_run
Definition: FERS_Registers_520X.h:652
picoTDC_Cfg_t::reg
uint32_t reg
Definition: FERS_Registers_520X.h:403
picoTDC_Cfg_t::parity
uint32_t parity
Definition: FERS_Registers_520X.h:745
picoTDC_Cfg_t::rx_en_bxrst
uint32_t rx_en_bxrst
Definition: FERS_Registers_520X.h:419
picoTDC_Cfg_t::eventid_offset
uint32_t eventid_offset
Definition: FERS_Registers_520X.h:492
picoTDC_Cfg_t::hrx_bot_en
uint32_t hrx_bot_en
Definition: FERS_Registers_520X.h:538
picoTDC_Cfg_t::tx_strenght
uint32_t tx_strenght
Definition: FERS_Registers_520X.h:539
picoTDC_Cfg_t::scan_out
uint32_t scan_out
Definition: FERS_Registers_520X.h:709
picoTDC_Cfg_t::errorcnts_reset
uint32_t errorcnts_reset
Definition: FERS_Registers_520X.h:398
picoTDC_Cfg_t::shift_clk80M
uint32_t shift_clk80M
Definition: FERS_Registers_520X.h:630
picoTDC_Cfg_t::trigger_buffer_size
uint32_t trigger_buffer_size
Definition: FERS_Registers_520X.h:515
picoTDC_Cfg_t::shift_clk1G28
uint32_t shift_clk1G28
Definition: FERS_Registers_520X.h:625
picoTDC_Cfg_t::bx_rst_ext_en
uint32_t bx_rst_ext_en
Definition: FERS_Registers_520X.h:414
picoTDC_Cfg_t::ch_parity
uint32_t ch_parity
Definition: FERS_Registers_520X.h:708
picoTDC_Cfg_t::pll_vco_igen_start
uint32_t pll_vco_igen_start
Definition: FERS_Registers_520X.h:585
picoTDC_Cfg_t::bunchcount_overflow
uint32_t bunchcount_overflow
Definition: FERS_Registers_520X.h:480
picoTDC_Cfg_t::eid_rst_ext_en
uint32_t eid_rst_ext_en
Definition: FERS_Registers_520X.h:415
picoTDC_Cfg_t::pll_afcvcal
uint32_t pll_afcvcal
Definition: FERS_Registers_520X.h:589
picoTDC_Cfg_t::dll_bias_val
uint32_t dll_bias_val
Definition: FERS_Registers_520X.h:547
picoTDC_Cfg_t::pll_afc_override
uint32_t pll_afc_override
Definition: FERS_Registers_520X.h:592
picoTDC_Cfg_t::dll_ctrlval
uint32_t dll_ctrlval
Definition: FERS_Registers_520X.h:550
picoTDC_Cfg_t::scan_in_tm
uint32_t scan_in_tm
Definition: FERS_Registers_520X.h:504
picoTDC_Cfg_t::pll_cp_mmdir
uint32_t pll_cp_mmdir
Definition: FERS_Registers_520X.h:572
picoTDC_Cfg_t::untriggered
uint32_t untriggered
Definition: FERS_Registers_520X.h:433
picoTDC_Cfg_t::hrx_bot_filter_trailing
uint32_t hrx_bot_filter_trailing
Definition: FERS_Registers_520X.h:535
picoTDC_Cfg_t::tot_8bit
uint32_t tot_8bit
Definition: FERS_Registers_520X.h:469
picoTDC_Cfg_t::rx_en_trigger
uint32_t rx_en_trigger
Definition: FERS_Registers_520X.h:421
picoTDC_Cfg_t::reserved3
uint32_t reserved3
Definition: FERS_Registers_520X.h:416
picoTDC_Cfg_t::magic_word
uint32_t magic_word
Definition: FERS_Registers_520X.h:393
picoTDC_Cfg_t::tr_dropped
uint32_t tr_dropped
Definition: FERS_Registers_520X.h:720
picoTDC_Cfg_t::pll_sw_ext
uint32_t pll_sw_ext
Definition: FERS_Registers_520X.h:575
picoTDC_Cfg_t::pg_ini
uint32_t pg_ini
Definition: FERS_Registers_520X.h:655
picoTDC_Cfg_t::dropcnts_reset
uint32_t dropcnts_reset
Definition: FERS_Registers_520X.h:397
picoTDC_Cfg_t::header_fields0
uint32_t header_fields0
Definition: FERS_Registers_520X.h:440
picoTDC_Cfg_t::pll_afcstart
uint32_t pll_afcstart
Definition: FERS_Registers_520X.h:590
picoTDC_Cfg_t::pg_en
uint32_t pg_en
Definition: FERS_Registers_520X.h:656
picoTDC_Cfg_t::falling_en
uint32_t falling_en
Definition: FERS_Registers_520X.h:409
picoTDC_Cfg_t::pll_cp_dacset
uint32_t pll_cp_dacset
Definition: FERS_Registers_520X.h:569
picoTDC_Cfg_t::ro_multibiterr
uint32_t ro_multibiterr
Definition: FERS_Registers_520X.h:736
picoTDC_Cfg_t::pll_selectedcap
uint32_t pll_selectedcap
Definition: FERS_Registers_520X.h:752
picoTDC_Cfg_t::channel_buffer_size
uint32_t channel_buffer_size
Definition: FERS_Registers_520X.h:513
picoTDC_Cfg_t::pll_cp_irefcpset
uint32_t pll_cp_irefcpset
Definition: FERS_Registers_520X.h:570
picoTDC_Cfg_t::pg_falling
uint32_t pg_falling
Definition: FERS_Registers_520X.h:668
picoTDC_Cfg_t::header_fields2
uint32_t header_fields2
Definition: FERS_Registers_520X.h:444
picoTDC_Cfg_t::dll_fixctrl
uint32_t dll_fixctrl
Definition: FERS_Registers_520X.h:551
picoTDC_Cfg_t::hrx_top_filter_trailing
uint32_t hrx_top_filter_trailing
Definition: FERS_Registers_520X.h:529
picoTDC_Cfg_t::error_flags_3
uint32_t error_flags_3
Definition: FERS_Registers_520X.h:686
picoTDC_Cfg_t::tot_startbit
uint32_t tot_startbit
Definition: FERS_Registers_520X.h:470
picoTDC_Cfg_t::readout_buffer_size
uint32_t readout_buffer_size
Definition: FERS_Registers_520X.h:514
picoTDC_Cfg_t::shift_clk320M_ref
uint32_t shift_clk320M_ref
Definition: FERS_Registers_520X.h:628
picoTDC_Cfg_t::pg_rising
uint32_t pg_rising
Definition: FERS_Registers_520X.h:659
picoTDC_Cfg_t::channel_enable
uint32_t channel_enable
Definition: FERS_Registers_520X.h:506
picoTDC_Cfg_t::pg_rep
uint32_t pg_rep
Definition: FERS_Registers_520X.h:653
picoTDC_Cfg_t::tg_bot_nen_fine
uint32_t tg_bot_nen_fine
Definition: FERS_Registers_520X.h:555
picoTDC_Cfg_t::trigger_create
uint32_t trigger_create
Definition: FERS_Registers_520X.h:399
picoTDC_Cfg_t::pll_cp_ce
uint32_t pll_cp_ce
Definition: FERS_Registers_520X.h:568
picoTDC_Cfg_t::hrx_enable_b
uint32_t hrx_enable_b
Definition: FERS_Registers_520X.h:645
picoTDC_Cfg_t::ch_fillgrade
uint32_t ch_fillgrade
Definition: FERS_Registers_520X.h:706
picoTDC_Cfg_t::pll_railmode_vco
uint32_t pll_railmode_vco
Definition: FERS_Registers_520X.h:586
picoTDC_Cfg_t::ext_clk_dll
uint32_t ext_clk_dll
Definition: FERS_Registers_520X.h:616
picoTDC_Cfg_t::trg_ch0_delay
uint32_t trg_ch0_delay
Definition: FERS_Registers_520X.h:466
picoTDC_Cfg_t::tot_saturate
uint32_t tot_saturate
Definition: FERS_Registers_520X.h:471
picoTDC_Cfg_t::dll_bias_cal
uint32_t dll_bias_cal
Definition: FERS_Registers_520X.h:548
picoTDC_Cfg_t::hrx_top_bias
uint32_t hrx_top_bias
Definition: FERS_Registers_520X.h:528
picoTDC_Cfg_t::scan_en_tm
uint32_t scan_en_tm
Definition: FERS_Registers_520X.h:503
picoTDC_Cfg_t::relative
uint32_t relative
Definition: FERS_Registers_520X.h:435
picoTDC_Cfg_t::tg_top_nen_coarse
uint32_t tg_top_nen_coarse
Definition: FERS_Registers_520X.h:558
picoTDC_Cfg_t::single_readout_en
uint32_t single_readout_en
Definition: FERS_Registers_520X.h:410
picoTDC_Cfg_t::hrx_top_filter_leading
uint32_t hrx_top_filter_leading
Definition: FERS_Registers_520X.h:530
picoTDC_Cfg_t::trigger_ch0_en
uint32_t trigger_ch0_en
Definition: FERS_Registers_520X.h:438
picoTDC_Cfg_t::hrx_enable_t
uint32_t hrx_enable_t
Definition: FERS_Registers_520X.h:638
picoTDC_Cfg_t::par_phase
uint32_t par_phase
Definition: FERS_Registers_520X.h:614
picoTDC_Cfg_t::disable_ro_reject
uint32_t disable_ro_reject
Definition: FERS_Registers_520X.h:516
picoTDC_Cfg_t::pll_afc_overrideval
uint32_t pll_afc_overrideval
Definition: FERS_Registers_520X.h:594
picoTDC_Cfg_t::pll_resistor
uint32_t pll_resistor
Definition: FERS_Registers_520X.h:574
picoTDC_Cfg_t::dig_rst_ext_en
uint32_t dig_rst_ext_en
Definition: FERS_Registers_520X.h:413
picoTDC_Cfg_t::pll_abuffdacset
uint32_t pll_abuffdacset
Definition: FERS_Registers_520X.h:587
picoTDC_Cfg_t::pll_vco_dacset
uint32_t pll_vco_dacset
Definition: FERS_Registers_520X.h:577
picoTDC_Cfg_t::pll_afcrst
uint32_t pll_afcrst
Definition: FERS_Registers_520X.h:591
picoTDC_Cfg_t::trigger_create_single
uint32_t trigger_create_single
Definition: FERS_Registers_520X.h:400
picoTDC_Cfg_t::reserved2
uint32_t reserved2
Definition: FERS_Registers_520X.h:411
picoTDC_Cfg_t::hrx_top_delay
uint32_t hrx_top_delay
Definition: FERS_Registers_520X.h:527
picoTDC_Cfg_t::pll_cp_mmcomp
uint32_t pll_cp_mmcomp
Definition: FERS_Registers_520X.h:571
picoTDC_Cfg_t::trigger_window
uint32_t trigger_window
Definition: FERS_Registers_520X.h:457
picoTDC_Cfg_t::pg_direct
uint32_t pg_direct
Definition: FERS_Registers_520X.h:654
picoTDC_Cfg_t::pll_afc_overridesig
uint32_t pll_afc_overridesig
Definition: FERS_Registers_520X.h:595
picoTDC_Cfg_t::reserved1
uint32_t reserved1
Definition: FERS_Registers_520X.h:401
picoTDC_Cfg_t::sync_clock
uint32_t sync_clock
Definition: FERS_Registers_520X.h:615
picoTDC_Cfg_t::max_eventsize
uint32_t max_eventsize
Definition: FERS_Registers_520X.h:448
picoTDC_Cfg_t::pg_reload
uint32_t pg_reload
Definition: FERS_Registers_520X.h:676
picoTDC_Cfg_t::eventid_reset
uint32_t eventid_reset
Definition: FERS_Registers_520X.h:396
picoTDC_Cfg_t::hrx_top_en
uint32_t hrx_top_en
Definition: FERS_Registers_520X.h:532
picoTDC_Cfg_t::tr_stateerr
uint32_t tr_stateerr
Definition: FERS_Registers_520X.h:723
picoTDC_Cfg_t::tg_top_nen_fine
uint32_t tg_top_nen_fine
Definition: FERS_Registers_520X.h:557
picoTDC_Cfg_t::hit_phase
uint32_t hit_phase
Definition: FERS_Registers_520X.h:604
picoTDC_Cfg_t::par_speed
uint32_t par_speed
Definition: FERS_Registers_520X.h:612
picoTDC_Cfg_t::digital_reset
uint32_t digital_reset
Definition: FERS_Registers_520X.h:394
picoTDC_Cfg_t::channel_split2
uint32_t channel_split2
Definition: FERS_Registers_520X.h:424