| CAEN FERS Library v1.1.4 SDK for FERS systems

FERS_config.h
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1
17#ifndef _FERSCFG_H
18#define _FERSCFG_H // Protect against multiple inclusion
19
20// _Thread_local is C11 with thread support
21#if (__STDC_VERSION__ >= 201112L) && !defined(__STDC_NO_THREADS__)
22#define THREAD_LOCAL _Thread_local
23#elif defined(_WIN32)
24#define THREAD_LOCAL __declspec(thread)
25#elif defined(__GNUC__)
26#define THREAD_LOCAL __thread
27#else
28#error unsupported compiler
29#endif
30
31#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
32
33#include "FERSlib.h"
34#include "FERS_MultiPlatform.h"
35#include "FERS_Registers_520X.h"
36#include "FERS_Registers_5215.h"
37
41// ***************************************************************************
42// Variables
43// ***************************************************************************
44 extern int BoardConnected[FERSLIB_MAX_NBRD]; // = { 0 }; // Board connection status
45 extern int NumBoardConnected; // = 0; // Number of boards connected
46 extern float CLK_PERIOD[FERSLIB_MAX_NBRD];
47 extern FERS_BoardInfo_t* FERS_BoardInfo[FERSLIB_MAX_NBRD]; // pointers to the board info structs
48 extern uint16_t MaxEnergyRange;
49 extern float TDL_FiberDelayAdjust[FERSLIB_MAX_NCNC][FERSLIB_MAX_NTDL][FERSLIB_MAX_NNODES];
54//****************************************************************************
55// struct that contains the configuration parameters (HW and SW)
56//****************************************************************************
62 typedef struct Config_t {
63
64 // Board mutex
65 mutex_t bmutex;
66
67 // System info
68 //char ConnPath[200]; // IP address of the board. Set by FERSlib_open
69 int handle;
70
71 // -------------------------------------------------------------
72 // Raw data parameters
73 // -------------------------------------------------------------
74 uint8_t OF_RawData;
75 uint8_t OF_LimitedSize;
76 float MaxSizeDataOutputFile;
77 char OF_RawDataPath[200];
78
79 // -------------------------------------------------------------
80 // Settings for the acquisition modes and I/O masks
81 // -------------------------------------------------------------
82 int AcquisitionMode;
83 int StartRunMode;
84 int StopRunMode;
85 uint32_t TestMode;
86
87 uint32_t TriggerMask;
88 uint32_t T0_outMask;
89 uint32_t T1_outMask;
90 uint32_t Tref_Mask;
91 uint32_t Veto_Mask;
92 uint32_t Validation_Mask;
93 uint32_t Validation_Mode;
94 uint32_t Counting_Mode;
95 uint32_t TrgIdMode;
96 uint32_t EnableServiceEvents;
97 uint32_t EnableCntZeroSuppr;
98 uint32_t Dis_tdl;
99 uint32_t EnableChannelTrgout;
100 uint32_t Enable_2nd_tstamp;
101 uint32_t EnableToT;
102 uint32_t WaveformLength;
103 uint32_t WaveformSource;
104 uint32_t Range_14bit;
105 uint32_t En_Empty_Ev_Suppr;
106 float GateWidth;
107 float TrefWindow;
108 float TrefDelay;
109 float PtrgPeriod;
110 float TrgHoldOff;
111
112 // -------------------------------------------------------------
113 // Settings for Channel enabling
114 // -------------------------------------------------------------
115 uint64_t ChEnableMask;
116 uint64_t ChEnableMask_e;
117
118 // -------------------------------------------------------------
119 // Settings for analog and digital probes
120 // -------------------------------------------------------------
121 uint32_t AnalogProbe[2];
122 uint32_t DigitalProbe[2];
123 uint32_t ProbeChannel[2];
124
125 // -------------------------------------------------------------
126 // Settings for DT5215 (Concentrator)
127 // -------------------------------------------------------------
128 float FiberDelayAdjust[FERSLIB_MAX_NCNC][8][16];
129 uint32_t TdlClkPhase;
130 uint32_t MaxPck_Block;
131 uint32_t MaxPck_Train;
132 uint32_t CncBufferSize;
133 uint32_t CncProbe_A;
134 uint32_t CncProbe_B;
135
136 // -------------------------------------------------------------
137 // Settings for FPGA trigger logic
138 // -------------------------------------------------------------
139 uint64_t Tlogic_Mask;
140 uint32_t TriggerLogic;
141 uint32_t MajorityLevel;
142 float ChTrg_Width;
143 float Tlogic_Width;
144
145 // -------------------------------------------------------------
146 // Settings for XROC ASICs
147 // -------------------------------------------------------------
148 uint16_t ZS_Threshold_LG[FERSLIB_MAX_NCH_5202];
149 uint16_t ZS_Threshold_HG[FERSLIB_MAX_NCH_5202];
150 uint16_t QD_FineThreshold[FERSLIB_MAX_NCH_5202];
151 uint16_t TD_FineThreshold[FERSLIB_MAX_NCH_5202];
152 uint16_t HG_Gain[FERSLIB_MAX_NCH_5202];
153 uint16_t LG_Gain[FERSLIB_MAX_NCH_5202];
154 uint16_t PAQ_Gain[FERSLIB_MAX_NCH_5204];
155 uint16_t PAQ_Comp[FERSLIB_MAX_NCH_5204];
156 uint16_t HV_IndivAdj[FERSLIB_MAX_NCH_5202];
157 uint16_t InputPolarity[FERSLIB_MAX_NCH_5204];
158 uint64_t QD_Mask;
159 uint64_t TD1_Mask;
160 uint64_t TD2_Mask;
161 uint64_t TD_Mask;
162 uint64_t TOTD_Mask;
163 uint32_t TD_CoarseThreshold;
164 uint32_t HG_ShapingTime;
165 uint32_t LG_ShapingTime;
166 uint32_t Enable_HV_Adjust;
167 uint16_t HV_Adjust_Range;
168 uint16_t T_Gain[FERSLIB_MAX_NCH_5204];
169 uint16_t TD1_CoarseThreshold;
170 uint16_t TD2_CoarseThreshold;
171 uint16_t TOTD_CoarseThreshold;
172 uint16_t QD_CoarseThreshold;
173 uint16_t TD1_FineThreshold[FERSLIB_MAX_NCH_5204];
174 uint16_t TD2_FineThreshold[FERSLIB_MAX_NCH_5204];
175 uint16_t TOTD_FineThreshold[FERSLIB_MAX_NCH_5204];
176 uint16_t HG_ShapingTime_ind[FERSLIB_MAX_NCH_5204];
177 uint16_t LG_ShapingTime_ind[FERSLIB_MAX_NCH_5204];
178 uint32_t PeakDetectorMode;
179 uint32_t EnableQdiscrLatch;
180 uint32_t FastShaperInput;
181 uint32_t TestPulsePreamp;
182 int TestPulseDestination;
183 uint32_t CitirocCfgMode;
184 float HoldDelay;
185 float MuxClkPeriod;
186 uint32_t MuxNSmean;
187 uint32_t GainSelect;
188 uint16_t Pedestal;
189
190 // -------------------------------------------------------------
191 // Settings for Analog Test Pulser
192 // -------------------------------------------------------------
193 int TestPulseSource;
194 uint32_t TestPulseAmplitude;
195
196
197 // -------------------------------------------------------------
198 // Settings for HV
199 // -------------------------------------------------------------
200 float HV_Vbias;
201 float HV_Imax;
202 float TempSensCoeff[3];
203 float TempFeedbackCoeff;
204 int EnableTempFeedback;
205
206
207 // -------------------------------------------------------------
208 // Settings for picoTDC
209 // -------------------------------------------------------------
210 uint32_t MeasMode;
211 uint32_t En_Head_Trail;
212 uint32_t HighResClock;
213 uint32_t GlitchFilterDelay;
214 uint32_t GlitchFilterMode;
215 uint32_t TDC_ChBufferSize;
216 uint32_t TriggerBufferSize;
217 uint32_t HeaderField0;
218 uint32_t HeaderField1;
219 uint32_t LeadTrail_LSB;
220 uint32_t ToT_LSB;
221 uint16_t ToT_reject_low_thr;
222 uint16_t ToT_reject_high_thr;
223 float TrgWindowWidth;
224 float TrgWindowOffset;
225 //uint8_t En_128_ch; //!< Enable 128 channels
226 float TDCpulser_Width;
227 float TDCpulser_Period;
228 uint32_t Ch_Offset[FERSLIB_MAX_NCH_5203];
229 //uint8_t InvertEdgePolarity[MAX_NCH]; //!< Invert edge polarity. NOTE: can be used in LEAD_TRAIL mode only
230
231
232 // -------------------------------------------------------------
233 // Settings for Adapters (A5256)
234 // -------------------------------------------------------------
235 int AdapterType; // MISSING in CFG //!< Adapter Type
236 float DiscrThreshold[FERSLIB_MAX_NCH_5203];
237 float DiscrThreshold2[FERSLIB_MAX_NCH_5203];
238 int DisableThresholdCalib;
239 int A5256_Ch0Polarity;
240
241
242 // -------------------------------------------------------------
243 // Generic write accesses
244 // -------------------------------------------------------------
245 int GWn;
246 uint32_t GWaddr[FERSLIB_MAX_GW];
247 uint32_t GWdata[FERSLIB_MAX_GW];
248 uint32_t GWmask[FERSLIB_MAX_GW];
249
250} Config_t;
253 extern Config_t* FERScfg[FERSLIB_MAX_NBRD]; // Configuration parameters
254
255
259//****************************************************************************
260// Functions
261//****************************************************************************
262 int Configure5202(int handle, int mode);
263 int Configure5203(int handle, int mode);
264 int Configure5204(int handle, int mode);
265 int FERS_DumpBoardRegister5202(int handle, char* filename);
266 int FERS_DumpBoardRegister5203(int handle, char* filename);
267 int FERS_DumpBoardRegister5204(int handle, char* filename);
268 int ConfigureProbe5202(int handle);
269 int ConfigureProbe5203(int handle);
270 int ConfigureProbe5204(int handle);
271 void Set_picoTDC_Default(picoTDC_Cfg_t* pcfg);
272 int Write_picoTDC_Cfg(int handle, int tdc, picoTDC_Cfg_t pcfg, int skipch);
273 int Read_picoTDC_Cfg(int handle, int tdc, picoTDC_Cfg_t* pcfg);
274 int Save_picoTDC_Cfg(int handle, int tdc, char* fname);
279#endif
FERSlib.h
CAEN FERS Library.
FERSLIB_MAX_GW
#define FERSLIB_MAX_GW
Definition: FERSlib.h:461
FERScfg
Config_t * FERScfg[128]
FERS_Registers_5215.h
FERS_Registers_520X.h
FERSLIB_MAX_NTDL
#define FERSLIB_MAX_NTDL
Definition: FERSlib.h:132
FERSLIB_MAX_NNODES
#define FERSLIB_MAX_NNODES
Definition: FERSlib.h:133
FERSLIB_MAX_NBRD
#define FERSLIB_MAX_NBRD
Definition: FERSlib.h:126
FERSLIB_MAX_NCNC
#define FERSLIB_MAX_NCNC
Definition: FERSlib.h:125
FERSLIB_MAX_NCH_5202
#define FERSLIB_MAX_NCH_5202
Definition: FERSlib.h:128
FERSLIB_MAX_NCH_5203
#define FERSLIB_MAX_NCH_5203
Definition: FERSlib.h:129
FERSLIB_MAX_NCH_5204
#define FERSLIB_MAX_NCH_5204
Definition: FERSlib.h:130
FERS_BoardInfo_t
FERS board information structure.
Definition: FERSlib.h:530
Config_t
FERS configuration parameters structure (lib + board)
Definition: FERS_config.h:62
Config_t::A5256_Ch0Polarity
int A5256_Ch0Polarity
Polarity of Ch0 in A5256 (POS, NEG)
Definition: FERS_config.h:239
Config_t::PAQ_Gain
uint16_t PAQ_Gain[64]
Gain of the Charge Preamp (Psiroc)
Definition: FERS_config.h:154
Config_t::GlitchFilterMode
uint32_t GlitchFilterMode
DISABLED, TRAILING, LEADING, BOTH.
Definition: FERS_config.h:214
Config_t::HeaderField0
uint32_t HeaderField0
Header Field0 (for test only, default=4=near full flags (ch 0..7 of the port) - 00000CCCCCCCC)
Definition: FERS_config.h:217
Config_t::GWaddr
uint32_t GWaddr[20]
Register Address.
Definition: FERS_config.h:246
Config_t::MuxNSmean
uint32_t MuxNSmean
Num of samples for the Mux mean: 0: 4 samples, 1: 16 samples.
Definition: FERS_config.h:186
Config_t::TestMode
uint32_t TestMode
Run with fixed data patterns generated by the FPGA.
Definition: FERS_config.h:85
Config_t::StopRunMode
int StopRunMode
Stop Mode (for now, stop is always controlled by SW, but in the future it might be implemented in HW)
Definition: FERS_config.h:84
Config_t::Validation_Mode
uint32_t Validation_Mode
Validation Mode: 0=disabled, 1=positive (accept), 2=negative (reject)
Definition: FERS_config.h:93
Config_t::T0_outMask
uint32_t T0_outMask
T0-OUT mask.
Definition: FERS_config.h:88
Config_t::TrefDelay
float TrefDelay
Tref delay in ns (can be negative)
Definition: FERS_config.h:108
Config_t::EnableServiceEvents
uint32_t EnableServiceEvents
Enable service events.
Definition: FERS_config.h:96
Config_t::ZS_Threshold_HG
uint16_t ZS_Threshold_HG[64]
Low Threshold for zero suppression (HG)
Definition: FERS_config.h:149
Config_t::TriggerLogic
uint32_t TriggerLogic
Trigger Logic Definition.
Definition: FERS_config.h:140
Config_t::AnalogProbe
uint32_t AnalogProbe[2]
Analog probe in XROC ASICs (Preamp LG/HG, Slow Shaper HG/LG, Fast Shaper)
Definition: FERS_config.h:121
Config_t::AcquisitionMode
int AcquisitionMode
Acquisition mode (Spectroscopy, Timing, Counting, etc...). Options are board dependent.
Definition: FERS_config.h:82
Config_t::CncProbe_B
uint32_t CncProbe_B
Digital Probe in the concentrator (output FB)
Definition: FERS_config.h:134
Config_t::DisableThresholdCalib
int DisableThresholdCalib
Disable threshold calibration.
Definition: FERS_config.h:238
Config_t::WaveformLength
uint32_t WaveformLength
Num of samples in the waveform.
Definition: FERS_config.h:102
Config_t::PeakDetectorMode
uint32_t PeakDetectorMode
Peaking Mode: 0 = Peak Stretcher, 1 = Track&Hold.
Definition: FERS_config.h:178
Config_t::TD2_Mask
uint64_t TD2_Mask
Enable mask of Time Discriminator 2.
Definition: FERS_config.h:160
Config_t::PAQ_Comp
uint16_t PAQ_Comp[64]
Gain of the Charge Preamp (Psiroc)
Definition: FERS_config.h:155
Config_t::LG_Gain
uint16_t LG_Gain[64]
Gain of the Low Gain Preamp.
Definition: FERS_config.h:153
Config_t::ChTrg_Width
float ChTrg_Width
Self Trg Width in ns => Coinc windows for paired counting and trigger logic.
Definition: FERS_config.h:142
Config_t::handle
int handle
Definition: FERS_config.h:69
Config_t::ToT_reject_high_thr
uint16_t ToT_reject_high_thr
The FPGA suppresses the Hits with ToT < high_threshold (0 disabled)
Definition: FERS_config.h:222
Config_t::HV_IndivAdj
uint16_t HV_IndivAdj[64]
HV individual bias adjust (Citiroc 8bit input DAC)
Definition: FERS_config.h:156
Config_t::MaxPck_Block
uint32_t MaxPck_Block
Max. number of packets (events) that the concentrator can aggregate in one Data Block (0 = use defaul...
Definition: FERS_config.h:130
Config_t::MeasMode
uint32_t MeasMode
LEAD_ONLY, LEAD_TRAIL, LEAD_TOT8, LEAD_TOT11.
Definition: FERS_config.h:210
Config_t::TempFeedbackCoeff
float TempFeedbackCoeff
Temperature Feedback Coeff: Vout = Vset - k * (T-25)
Definition: FERS_config.h:203
Config_t::Enable_2nd_tstamp
uint32_t Enable_2nd_tstamp
Enable 2nd time stamp relative to the Tref signal.
Definition: FERS_config.h:100
Config_t::QD_FineThreshold
uint16_t QD_FineThreshold[64]
Fine Threshold for Citiroc charge discriminator.
Definition: FERS_config.h:150
Config_t::MaxPck_Train
uint32_t MaxPck_Train
Max. number of packets (events) that the FERS unit can transmit to the concentrator in a single data ...
Definition: FERS_config.h:131
Config_t::LeadTrail_LSB
uint32_t LeadTrail_LSB
Leading/Trailing LSB required by the user: 0: LSB = ~3ps, N: LSB = 3ps * 2^N, (Max N=10; LSB = ~3....
Definition: FERS_config.h:219
Config_t::LG_ShapingTime
uint32_t LG_ShapingTime
Shaping Time of the Low Gain preamp.
Definition: FERS_config.h:165
Config_t::OF_LimitedSize
uint8_t OF_LimitedSize
Enable limited size on raw data output files.
Definition: FERS_config.h:75
Config_t::WaveformSource
uint32_t WaveformSource
LG0, HG0, LG1, HG1 (High/Low Gain, chip 0/1)
Definition: FERS_config.h:103
Config_t::TD1_FineThreshold
uint16_t TD1_FineThreshold[64]
Fine Threshold for Time discriminator 1.
Definition: FERS_config.h:173
Config_t::EnableToT
uint32_t EnableToT
Enable readout of ToT (time over threshold) in A5202.
Definition: FERS_config.h:101
Config_t::Dis_tdl
uint32_t Dis_tdl
Enable the TDL switching off when not used (DNIN: why is a parameter?)
Definition: FERS_config.h:98
Config_t::Tlogic_Width
float Tlogic_Width
TriggerLogic output width (0=linear)
Definition: FERS_config.h:143
Config_t::ChEnableMask
uint64_t ChEnableMask
Channel enable mask (64 ch)
Definition: FERS_config.h:115
Config_t::FastShaperInput
uint32_t FastShaperInput
Fast Shaper (Tdiscr) connection: 0 = High Gain PA, 1 = Low Gain PA.
Definition: FERS_config.h:180
Config_t::EnableCntZeroSuppr
uint32_t EnableCntZeroSuppr
Enable zero suppression in Counting Mode.
Definition: FERS_config.h:97
Config_t::Tlogic_Mask
uint64_t Tlogic_Mask
Trigger Logic enable mask.
Definition: FERS_config.h:139
Config_t::ChEnableMask_e
uint64_t ChEnableMask_e
Channel enable mask of Mezzanine expansion (128 ch, A5203 only)
Definition: FERS_config.h:116
Config_t::GWn
int GWn
Definition: FERS_config.h:245
Config_t::Veto_Mask
uint32_t Veto_Mask
Veto mask.
Definition: FERS_config.h:91
Config_t::StartRunMode
int StartRunMode
Start Mode (this is a HW setting that defines how to start/stop the acquisition in the boards)
Definition: FERS_config.h:83
Config_t::TDCpulser_Period
float TDCpulser_Period
picoTDC Pulser Output (period in ns)
Definition: FERS_config.h:227
Config_t::QD_CoarseThreshold
uint16_t QD_CoarseThreshold
Coarse Threshold for Charge discriminator.
Definition: FERS_config.h:172
Config_t::TD_CoarseThreshold
uint32_t TD_CoarseThreshold
Coarse Threshold for Citiroc time discriminator.
Definition: FERS_config.h:163
Config_t::QD_Mask
uint64_t QD_Mask
Enable mask of Charge Discriminator.
Definition: FERS_config.h:158
Config_t::bmutex
mutex_t bmutex
Definition: FERS_config.h:65
Config_t::HV_Vbias
float HV_Vbias
Voltage setting for HV.
Definition: FERS_config.h:200
Config_t::TD2_FineThreshold
uint16_t TD2_FineThreshold[64]
Fine Threshold for Time discriminator 2.
Definition: FERS_config.h:174
Config_t::GateWidth
float GateWidth
Gate window width in ns (will be rounded to steps of 25 ns)
Definition: FERS_config.h:106
Config_t::HeaderField1
uint32_t HeaderField1
Header Field1 (for test only, default=5=near full flags (ch 8..15 of the port + RO_buff,...
Definition: FERS_config.h:218
Config_t::Ch_Offset
uint32_t Ch_Offset[128]
Channel Offset.
Definition: FERS_config.h:228
Config_t::TDCpulser_Width
float TDCpulser_Width
picoTDC Pulser Output (width in ns)
Definition: FERS_config.h:226
Config_t::HG_ShapingTime
uint32_t HG_ShapingTime
Shaping Time of the High Gain preamp.
Definition: FERS_config.h:164
Config_t::GWdata
uint32_t GWdata[20]
Data to write.
Definition: FERS_config.h:247
Config_t::Counting_Mode
uint32_t Counting_Mode
Counting Mode (Singles, Paired_AND)
Definition: FERS_config.h:94
Config_t::Enable_HV_Adjust
uint32_t Enable_HV_Adjust
Enable input DAC for HV fine adjust.
Definition: FERS_config.h:166
Config_t::DiscrThreshold
float DiscrThreshold[128]
Discriminator Threshold.
Definition: FERS_config.h:236
Config_t::TriggerMask
uint32_t TriggerMask
Bunch Trigger mask.
Definition: FERS_config.h:87
Config_t::Range_14bit
uint32_t Range_14bit
Use full 14 bit range for the A/D conversion.
Definition: FERS_config.h:104
Config_t::ProbeChannel
uint32_t ProbeChannel[2]
Channel to probe.
Definition: FERS_config.h:123
Config_t::DiscrThreshold2
float DiscrThreshold2[128]
Discriminator 2nd Threshold (double thershold mode only)
Definition: FERS_config.h:237
Config_t::TrgWindowOffset
float TrgWindowOffset
Trigger window offset in ns; can be negative (will be rounded to steps of 25 ns)
Definition: FERS_config.h:224
Config_t::LG_ShapingTime_ind
uint16_t LG_ShapingTime_ind[64]
Shaping Time of the Low Gain preamp (individual)
Definition: FERS_config.h:177
Config_t::DigitalProbe
uint32_t DigitalProbe[2]
Digital probe in XROC ASICs (peak Sens HG/LG) or FPGA (start_conv, data_commit...)
Definition: FERS_config.h:122
Config_t::GainSelect
uint32_t GainSelect
Select gain between High/Low/Auto.
Definition: FERS_config.h:187
Config_t::TD2_CoarseThreshold
uint16_t TD2_CoarseThreshold
Coarse Threshold for Time discriminator 2.
Definition: FERS_config.h:170
Config_t::TestPulseSource
int TestPulseSource
EXT, INT_T0, INT_T1, INT_PTRG, INT_SW.
Definition: FERS_config.h:193
Config_t::HighResClock
uint32_t HighResClock
High Res clock distribution (MCX connectors)
Definition: FERS_config.h:212
Config_t::TrgHoldOff
float TrgHoldOff
Retrigger protection time. Set the busy active for N clock cycles (0=disabled)
Definition: FERS_config.h:110
Config_t::TOTD_Mask
uint64_t TOTD_Mask
Enable mask of TOT Discriminator (Psiroc)
Definition: FERS_config.h:162
Config_t::AdapterType
int AdapterType
Definition: FERS_config.h:235
Config_t::TestPulsePreamp
uint32_t TestPulsePreamp
1=LG, 2=HG, 3=BOTH
Definition: FERS_config.h:181
Config_t::T_Gain
uint16_t T_Gain[64]
T-Preamp gain.
Definition: FERS_config.h:168
Config_t::TD1_Mask
uint64_t TD1_Mask
Enable mask of Time Discriminator 1.
Definition: FERS_config.h:159
Config_t::InputPolarity
uint16_t InputPolarity[64]
Preamp Input Polarity.
Definition: FERS_config.h:157
Config_t::OF_RawDataPath
char OF_RawDataPath[200]
Raw data files saving path.
Definition: FERS_config.h:77
Config_t::PtrgPeriod
float PtrgPeriod
period in ns of the internal periodic trigger (dwell time)
Definition: FERS_config.h:109
Config_t::T1_outMask
uint32_t T1_outMask
T1-OUT mask.
Definition: FERS_config.h:89
Config_t::En_Empty_Ev_Suppr
uint32_t En_Empty_Ev_Suppr
Enable event suppression (only in Custom header mode)
Definition: FERS_config.h:105
Config_t::HG_ShapingTime_ind
uint16_t HG_ShapingTime_ind[64]
Shaping Time of the High Gain preamp (individual)
Definition: FERS_config.h:176
Config_t::EnableChannelTrgout
uint32_t EnableChannelTrgout
0 = Channel Trgout Disabled, 1 = Enabled (used in Citiroc only)
Definition: FERS_config.h:99
Config_t::TriggerBufferSize
uint32_t TriggerBufferSize
Size of the trigger buffer in the FPGA (limits the number or pending triggers, already sent to the TD...
Definition: FERS_config.h:216
Config_t::FiberDelayAdjust
float FiberDelayAdjust[4][8][16]
Fiber length (in meters) for individual tuning of the propagation delay along the TDL daisy chains.
Definition: FERS_config.h:128
Config_t::TD_FineThreshold
uint16_t TD_FineThreshold[64]
Fine Threshold for Citiroc time discriminator.
Definition: FERS_config.h:151
Config_t::HV_Adjust_Range
uint16_t HV_Adjust_Range
HV adj DAC range (reference): 0 = 2.5V, 1 = 4.5V, ?=DISABLED.
Definition: FERS_config.h:167
Config_t::CncProbe_A
uint32_t CncProbe_A
Digital Probe in the concentrator (output FA)
Definition: FERS_config.h:133
Config_t::TrgWindowWidth
float TrgWindowWidth
Trigger window width in ns (will be rounded to steps of 25 ns)
Definition: FERS_config.h:223
Config_t::EnableQdiscrLatch
uint32_t EnableQdiscrLatch
Q-dicr mode: 1 = Latched, 0 = Direct.
Definition: FERS_config.h:179
Config_t::Tref_Mask
uint32_t Tref_Mask
Tref mask
Definition: FERS_config.h:90
Config_t::MuxClkPeriod
float MuxClkPeriod
Period of the Mux Clock.
Definition: FERS_config.h:185
Config_t::Pedestal
uint16_t Pedestal
Common pedestal added to all channels.
Definition: FERS_config.h:188
Config_t::En_Head_Trail
uint32_t En_Head_Trail
Enable Header and Trailer: 0=Keep all (group header+trail), 1=One word, 2=Header and trailer suppress...
Definition: FERS_config.h:211
Config_t::CncBufferSize
uint32_t CncBufferSize
Data buffer size (in 32 bit words) in the concentrator; stop trains when this level is reached (0 = u...
Definition: FERS_config.h:132
Config_t::ToT_reject_low_thr
uint16_t ToT_reject_low_thr
The FPGA suppresses the Hits with ToT > low_threshold (0 disabled)
Definition: FERS_config.h:221
Config_t::TOTD_FineThreshold
uint16_t TOTD_FineThreshold[64]
Fine Threshold for TOT discriminator.
Definition: FERS_config.h:175
Config_t::TD1_CoarseThreshold
uint16_t TD1_CoarseThreshold
Coarse Threshold for Time discriminator 1.
Definition: FERS_config.h:169
Config_t::HG_Gain
uint16_t HG_Gain[64]
Gain of the High Gain Preamp.
Definition: FERS_config.h:152
Config_t::CitirocCfgMode
uint32_t CitirocCfgMode
0=from regs, 1=from file
Definition: FERS_config.h:183
Config_t::TrefWindow
float TrefWindow
Tref Windows in ns (Common start/stop)
Definition: FERS_config.h:107
Config_t::ZS_Threshold_LG
uint16_t ZS_Threshold_LG[64]
Low Threshold for zero suppression (LG)
Definition: FERS_config.h:148
Config_t::TDC_ChBufferSize
uint32_t TDC_ChBufferSize
Channel buffer size in the picoTDC (set a limit to the max number of hits acquired by the channel)
Definition: FERS_config.h:215
Config_t::TdlClkPhase
uint32_t TdlClkPhase
Recovered clock phase shift: 0=0, 1=90, 2=180, 3=270.
Definition: FERS_config.h:129
Config_t::MajorityLevel
uint32_t MajorityLevel
Majority Level.
Definition: FERS_config.h:141
Config_t::TestPulseAmplitude
uint32_t TestPulseAmplitude
DAC setting for the internal test pulser (12 bit). Meaningless for TestPulseSource=EXT.
Definition: FERS_config.h:194
Config_t::ToT_LSB
uint32_t ToT_LSB
ToT LSB required by the user: 0: LSB = 3.125ps, N: LSB = 3.125ps * 2^N, (Max N=18; LSB = ~800 ns)
Definition: FERS_config.h:220
Config_t::HoldDelay
float HoldDelay
Time between Trigger and Hold.
Definition: FERS_config.h:184
Config_t::TestPulseDestination
int TestPulseDestination
-1=ALL, -2=EVEN, -3=ODD or channel number (0 to 63) for single channel pulsing
Definition: FERS_config.h:182
Config_t::TempSensCoeff
float TempSensCoeff[3]
Temperature Sensor Coefficients (2=quad, 1=lin, 0=offset)
Definition: FERS_config.h:202
Config_t::TD_Mask
uint64_t TD_Mask
Enable mask of Fast Shaper Discriminator (Psiroc)
Definition: FERS_config.h:161
Config_t::GWmask
uint32_t GWmask[20]
Bit Mask.
Definition: FERS_config.h:248
Config_t::MaxSizeDataOutputFile
float MaxSizeDataOutputFile
Maximum size writable for raw data output files in bytes. Minimum size allowed 1 MB.
Definition: FERS_config.h:76
Config_t::HV_Imax
float HV_Imax
Imax for HV.
Definition: FERS_config.h:201
Config_t::TrgIdMode
uint32_t TrgIdMode
Trigger ID: 0 = trigger counter, 1 = validation counter.
Definition: FERS_config.h:95
Config_t::OF_RawData
uint8_t OF_RawData
Enable saving raw data output files.
Definition: FERS_config.h:74
Config_t::Validation_Mask
uint32_t Validation_Mask
Validation mask.
Definition: FERS_config.h:92
Config_t::GlitchFilterDelay
uint32_t GlitchFilterDelay
Delay of the glitch filter (~800 ps to ~10 ns with 16 steps)
Definition: FERS_config.h:213
Config_t::EnableTempFeedback
int EnableTempFeedback
Enable Temp Feedback.
Definition: FERS_config.h:204
Config_t::TOTD_CoarseThreshold
uint16_t TOTD_CoarseThreshold
Coarse Threshold for TOT discriminator.
Definition: FERS_config.h:171
picoTDC_Cfg_t
Definition: FERS_Registers_520X.h:389