V1742

The CAEN Mod. V1742 is a 1-unit wide VME 6U module housing 32+2 Channel 12 bit 5 GS/s Switched Capacitor Digitizer sections. The input dynamic range is 1 Vpp on single-ended MCX coaxial connectors (16-bit DAC on each channel to control the DC Offset).

The digitizer is based on the Switched Capacitor Array DRS4 chip (Domino Ring Sampler). This technology relies on a series of 1024 capacitors (analog memory) in which the analog input signal is continuously sampled in a circular way.
The sampling frequency is 5 GHz by default and it can be programmed to 2.5 GHz, 1GHz, and 750 MHz. The analog to digital conversion is not simultaneous with the chip sampling phase, and it starts as soon as the trigger condition is met, thus producing a dead time of 110 μs in case only the analog inputs are digitized, 181 μs when also the fast trigger TRn is digitized. When the trigger stops the DRS4 chip sampling (holding phase), the analog memory buffer is frozen, and the cell content is made available to the 12 bit ADC for the digital conversion.
The digital memory allows to store subsequent events, even if the readout is not yet started. Moreover, since the digital memory buffers work like FIFOs, the readout activity from VME or Optical Link does not affect write operations of subsequent events.

The available trigger sources are:

• External Trigger, trigger on TRG-IN connector, common to all enabled groups.

• Fast (Low Latency) Local Trigger, trigger on TR0 and TR1 connectors, common to couples of groups. This mode is called “Fast” or “Low Latency” since the trigger latency to hold the DRS4 is reduced with respect to the external trigger. This trigger mode is convenient for high precision timing measurements, since the TRn can be digitized and reported in the output data to be used as time reference.

• Self-trigger, common to couples of groups. For each group is possible to select combination of channels (logic OR) that provide a trigger whenever the input crosses the threshold. This mode cannot be used at 5 GHz due to the trigger latency.

The module features the front panel CLK IN/CLK OUT connectors and an internal PLL for clock synthesis from internal/external references. V1742 supports multi-board synchronization allowing all DRS4s to be synchronized with a common clock source and ensuring Trigger Time Stamps alignment. Once synchronized, all data will be aligned and coherent across multiple V1742 boards.

The module is available with digital memory sizes of 128 event/ch or 1024 event/ch.

The VME interface of the module is VME64X compliant, and the data readout can be performed in several data transfer modes: BLT32, MBLT64 (up to 70 MB/s of transfer rate using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s of transfer rate). The built-in daisy chainable Optical Link is able to transfer data at 80 MB/s, thus it is possible to connect up to 8 boards to a single A4818 Controller, or up to 32 to a single A5818 Controller (4-link version).

Software available (Windows and Linux): CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

• CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.

Software for V1742 running Waveform Recording Firmware:

• CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.

The V1742 fits in the single-slot CAEN VME64X u-crate, which allows you to convert the VME digitizer into a desktop board for lab tests.