DT5204

FERS-5200 is a front‐end readout system designed for the readout of large detector arrays, such as SiPMs, multi‐anode PMTs, Silicon Strip detectors, Wire Chambers, GEMs, Gas Tubes and others. FERS‐5200 is a distributed and scalable system, where each unit is a small card that houses 64 or 128 channels. It features a detector specific Front-End interfaced to a common infrastructure that guarantees readout interfaces, slow control and synchronization. Typically, the front-end is based on ASIC chips that allow for high density, cost effective integration of multi-channel readout electronics into small size and low power modules. FERS is a flexible platform: combining the same back-end (i.e. readout architecture and interface) with different types of front-end to fit a wide range of detectors.

The DT5204  (and A5204, which is the naked version) is a member of the FERS-5200 family. It uses the Radioroc chip (produced by Weeroc) for the readout of SiPM detectors. Radioroc allows triggering down to 1/3 p.e. and provides dual-gain energy measurement with excellent Signal-to-Noise Ratio on the high gain (SNR over 10 for single p.e.) and large dynamic range on the low gain. Thanks to the programmable shaping time, that can be different for low and high gain, the Radioroc can perform Pulse Shape Discrimination with organic and inorganic scintillators coupled to SiPMs.

The DT5204 includes a High Voltage generator (up to +80V, 10 mA) for the SiPM biasing; a channel-by-channel 8-bit DAC contained in the Radioroc ASIC allows for fine adjustment of the SiPM bias voltage and SiPM gains homogenization. Besides the slow shaper + peak sensing chain for the acquisition in spectroscopy mode, Radioroc includes configurable fast pre-amplifiers followed by discriminators that can output 64 individual channel triggers with jitter as low as 55 ps FWHM on a single p.e. The individual channel triggers are connected to the FPGA, for photo-counting up to 200 MHz as well as for the implementation of coincidences, majority and topological acquisition triggers. The individual triggers are also connected to a picoTDC, an ASIC chip produced by CERN, implementing a 64 channel TDC with LSB = 3.125 ps, for very precise timing measurements. Time Over Threshold (ToT) can also be used to estimate the pulse height, making it possible to acquire time stamp and PHA with very low dead time and extremely high rate, without the need of the multiplexed A/D conversion.

For small setups a single DT5204 unit can be used stand alone, without any additional hardware, by simply connecting the unit to a PC via USB 2.0 or Ethernet 10/100BASE-T. For large readout systems, a flexible and scalable network of units can be created by means of the high speed optical link called TDlink. The TDlink system supports up to 128 FERS units to be connected to and managed by one DT5215 FERS Data Concentrator Module. The TDlink supports optical daisy chaining and provides slow control, high speed data readout, synchronization between the units (clock and sync distribution), as well as command broadcasting for triggers, time resets, etc.

The DT5204 is fully supported by the CAEN Janus 5204 Open Source software on Windows^® and Linux^®. Janus can run in console mode (C program, without graphics) or connected to a GUI written in Python. The GUI has configuration and run control panels that simplify the data acquisition management. Both console and GUI modes acquire data from multiple boards, manage configuration, event building, PHA and timing histograms (deltaT and/or ToT), display data statistics (hit rate, throughput, etc…), plot histograms, and save output, including spectra and list files with the acquired timing data.

A wide range of adapters and cables has been also specifically designed for FERS-5200 boards, in order to provide versatility of choice and the ability to remotely operate the detectors, a complete list is available here. The A5250 adapter is standardly mounted as rear panel of the DT5202. An alternative compatible adapter may be installed upon customer request.