FERS configuration parameters structure (lib + board) More...

#include <FERS_config.h>

Collaboration diagram for Config_t:

Data Fields
mutex_t	bmutex

int	handle

uint8_t	OF_RawData
	Enable saving raw data output files.

uint8_t	OF_LimitedSize
	Enable limited size on raw data output files.

float	MaxSizeDataOutputFile
	Maximum size writable for raw data output files in bytes. Minimum size allowed 1 MB.

char	OF_RawDataPath [200]
	Raw data files saving path.

int	AcquisitionMode
	Acquisition mode (Spectroscopy, Timing, Counting, etc...). Options are board dependent.

int	StartRunMode
	Start Mode (this is a HW setting that defines how to start/stop the acquisition in the boards)

int	StopRunMode
	Stop Mode (for now, stop is always controlled by SW, but in the future it might be implemented in HW)

uint32_t	TestMode
	Run with fixed data patterns generated by the FPGA.

uint32_t	TriggerMask
	Bunch Trigger mask.

uint32_t	T0_outMask
	T0-OUT mask.

uint32_t	T1_outMask
	T1-OUT mask.

uint32_t	Tref_Mask
	Tref mask.

uint32_t	Veto_Mask
	Veto mask.

uint32_t	Validation_Mask
	Validation mask.

uint32_t	Validation_Mode
	Validation Mode: 0=disabled, 1=positive (accept), 2=negative (reject)

uint32_t	Counting_Mode
	Counting Mode (Singles, Paired_AND)

uint32_t	TrgIdMode
	Trigger ID: 0 = trigger counter, 1 = validation counter.

uint32_t	EnableServiceEvents
	Enable service events.

uint32_t	EnableCntZeroSuppr
	Enable zero suppression in Counting Mode.

uint32_t	Dis_tdl
	Enable the TDL switching off when not used (DNIN: why is a parameter?)

uint32_t	EnableChannelTrgout
	0 = Channel Trgout Disabled, 1 = Enabled (used in Citiroc only)

uint32_t	Enable_2nd_tstamp
	Enable 2nd time stamp relative to the Tref signal.

uint32_t	EnableToT
	Enable readout of ToT (time over threshold) in A5202.

uint32_t	WaveformLength
	Num of samples in the waveform.

uint32_t	WaveformSource
	LG0, HG0, LG1, HG1 (High/Low Gain, chip 0/1)

uint32_t	Range_14bit
	Use full 14 bit range for the A/D conversion.

uint32_t	En_Empty_Ev_Suppr
	Enable event suppression (only in Custom header mode)

float	GateWidth
	Gate window width in ns (will be rounded to steps of 25 ns)

float	TrefWindow
	Tref Windows in ns (Common start/stop)

float	TrefDelay
	Tref delay in ns (can be negative)

float	PtrgPeriod
	period in ns of the internal periodic trigger (dwell time)

float	TrgHoldOff
	Retrigger protection time. Set the busy active for N clock cycles (0=disabled)

uint64_t	ChEnableMask
	Channel enable mask (64 ch)

uint64_t	ChEnableMask_e
	Channel enable mask of Mezzanine expansion (128 ch, A5203 only)

uint32_t	AnalogProbe [2]
	Analog probe in XROC ASICs (Preamp LG/HG, Slow Shaper HG/LG, Fast Shaper)

uint32_t	DigitalProbe [2]
	Digital probe in XROC ASICs (peak Sens HG/LG) or FPGA (start_conv, data_commit...)

uint32_t	ProbeChannel [2]
	Channel to probe.

float	FiberDelayAdjust [4][8][16]
	Fiber length (in meters) for individual tuning of the propagation delay along the TDL daisy chains.

uint32_t	TdlClkPhase
	Recovered clock phase shift: 0=0, 1=90, 2=180, 3=270.

uint32_t	MaxPck_Block
	Max. number of packets (events) that the concentrator can aggregate in one Data Block (0 = use default in FW)

uint32_t	MaxPck_Train
	Max. number of packets (events) that the FERS unit can transmit to the concentrator in a single data train (0 = use default in FW)

uint32_t	CncBufferSize
	Data buffer size (in 32 bit words) in the concentrator; stop trains when this level is reached (0 = use default in FW)

uint32_t	CncProbe_A
	Digital Probe in the concentrator (output FA)

uint32_t	CncProbe_B
	Digital Probe in the concentrator (output FB)

uint64_t	Tlogic_Mask
	Trigger Logic enable mask.

uint32_t	TriggerLogic
	Trigger Logic Definition.

uint32_t	MajorityLevel
	Majority Level.

float	ChTrg_Width
	Self Trg Width in ns => Coinc windows for paired counting and trigger logic.

float	Tlogic_Width
	TriggerLogic output width (0=linear)

uint16_t	ZS_Threshold_LG [64]
	Low Threshold for zero suppression (LG)

uint16_t	ZS_Threshold_HG [64]
	Low Threshold for zero suppression (HG)

uint16_t	QD_FineThreshold [64]
	Fine Threshold for Citiroc charge discriminator.

uint16_t	TD_FineThreshold [64]
	Fine Threshold for Citiroc time discriminator.

uint16_t	HG_Gain [64]
	Gain of the High Gain Preamp.

uint16_t	LG_Gain [64]
	Gain of the Low Gain Preamp.

uint16_t	PAQ_Gain [64]
	Gain of the Charge Preamp (Psiroc)

uint16_t	PAQ_Comp [64]
	Gain of the Charge Preamp (Psiroc)

uint16_t	HV_IndivAdj [64]
	HV individual bias adjust (Citiroc 8bit input DAC)

uint16_t	InputPolarity [64]
	Preamp Input Polarity.

uint64_t	QD_Mask
	Enable mask of Charge Discriminator.

uint64_t	TD1_Mask
	Enable mask of Time Discriminator 1.

uint64_t	TD2_Mask
	Enable mask of Time Discriminator 2.

uint64_t	TD_Mask
	Enable mask of Fast Shaper Discriminator (Psiroc)

uint64_t	TOTD_Mask
	Enable mask of TOT Discriminator (Psiroc)

uint32_t	TD_CoarseThreshold
	Coarse Threshold for Citiroc time discriminator.

uint32_t	HG_ShapingTime
	Shaping Time of the High Gain preamp.

uint32_t	LG_ShapingTime
	Shaping Time of the Low Gain preamp.

uint32_t	Enable_HV_Adjust
	Enable input DAC for HV fine adjust.

uint16_t	HV_Adjust_Range
	HV adj DAC range (reference): 0 = 2.5V, 1 = 4.5V, ?=DISABLED.

uint16_t	T_Gain [64]
	T-Preamp gain.

uint16_t	TD1_CoarseThreshold
	Coarse Threshold for Time discriminator 1.

uint16_t	TD2_CoarseThreshold
	Coarse Threshold for Time discriminator 2.

uint16_t	TOTD_CoarseThreshold
	Coarse Threshold for TOT discriminator.

uint16_t	QD_CoarseThreshold
	Coarse Threshold for Charge discriminator.

uint16_t	TD1_FineThreshold [64]
	Fine Threshold for Time discriminator 1.

uint16_t	TD2_FineThreshold [64]
	Fine Threshold for Time discriminator 2.

uint16_t	TOTD_FineThreshold [64]
	Fine Threshold for TOT discriminator.

uint16_t	HG_ShapingTime_ind [64]
	Shaping Time of the High Gain preamp (individual)

uint16_t	LG_ShapingTime_ind [64]
	Shaping Time of the Low Gain preamp (individual)

uint32_t	PeakDetectorMode
	Peaking Mode: 0 = Peak Stretcher, 1 = Track&Hold.

uint32_t	EnableQdiscrLatch
	Q-dicr mode: 1 = Latched, 0 = Direct.

uint32_t	FastShaperInput
	Fast Shaper (Tdiscr) connection: 0 = High Gain PA, 1 = Low Gain PA.

uint32_t	TestPulsePreamp
	1=LG, 2=HG, 3=BOTH

int	TestPulseDestination
	-1=ALL, -2=EVEN, -3=ODD or channel number (0 to 63) for single channel pulsing

uint32_t	CitirocCfgMode
	0=from regs, 1=from file

float	HoldDelay
	Time between Trigger and Hold.

float	MuxClkPeriod
	Period of the Mux Clock.

uint32_t	MuxNSmean
	Num of samples for the Mux mean: 0: 4 samples, 1: 16 samples.

uint32_t	GainSelect
	Select gain between High/Low/Auto.

uint16_t	Pedestal
	Common pedestal added to all channels.

int	TestPulseSource
	EXT, INT_T0, INT_T1, INT_PTRG, INT_SW.

uint32_t	TestPulseAmplitude
	DAC setting for the internal test pulser (12 bit). Meaningless for TestPulseSource=EXT.

float	HV_Vbias
	Voltage setting for HV.

float	HV_Imax
	Imax for HV.

float	TempSensCoeff [3]
	Temperature Sensor Coefficients (2=quad, 1=lin, 0=offset)

float	TempFeedbackCoeff
	Temperature Feedback Coeff: Vout = Vset - k * (T-25)

int	EnableTempFeedback
	Enable Temp Feedback.

uint32_t	MeasMode
	LEAD_ONLY, LEAD_TRAIL, LEAD_TOT8, LEAD_TOT11.

uint32_t	En_Head_Trail
	Enable Header and Trailer: 0=Keep all (group header+trail), 1=One word, 2=Header and trailer suppressed.

uint32_t	HighResClock
	High Res clock distribution (MCX connectors)

uint32_t	GlitchFilterDelay
	Delay of the glitch filter (~800 ps to ~10 ns with 16 steps)

uint32_t	GlitchFilterMode
	DISABLED, TRAILING, LEADING, BOTH.

uint32_t	TDC_ChBufferSize
	Channel buffer size in the picoTDC (set a limit to the max number of hits acquired by the channel)

uint32_t	TriggerBufferSize
	Size of the trigger buffer in the FPGA (limits the number or pending triggers, already sent to the TDC but not written in the output FIFO yet)

uint32_t	HeaderField0
	Header Field0 (for test only, default=4=near full flags (ch 0..7 of the port) - 00000CCCCCCCC)

uint32_t	HeaderField1
	Header Field1 (for test only, default=5=near full flags (ch 8..15 of the port + RO_buff, TrgBuff) - RT000CCCCCCCC)

uint32_t	LeadTrail_LSB
	Leading/Trailing LSB required by the user: 0: LSB = ~3ps, N: LSB = 3ps * 2^N, (Max N=10; LSB = ~3.125 ns)

uint32_t	ToT_LSB
	ToT LSB required by the user: 0: LSB = 3.125ps, N: LSB = 3.125ps * 2^N, (Max N=18; LSB = ~800 ns)

uint16_t	ToT_reject_low_thr
	The FPGA suppresses the Hits with ToT > low_threshold (0 disabled)

uint16_t	ToT_reject_high_thr
	The FPGA suppresses the Hits with ToT < high_threshold (0 disabled)

float	TrgWindowWidth
	Trigger window width in ns (will be rounded to steps of 25 ns)

float	TrgWindowOffset
	Trigger window offset in ns; can be negative (will be rounded to steps of 25 ns)

float	TDCpulser_Width
	picoTDC Pulser Output (width in ns)

float	TDCpulser_Period
	picoTDC Pulser Output (period in ns)

uint32_t	Ch_Offset [128]
	Channel Offset.

int	AdapterType

float	DiscrThreshold [128]
	Discriminator Threshold.

float	DiscrThreshold2 [128]
	Discriminator 2nd Threshold (double thershold mode only)

int	DisableThresholdCalib
	Disable threshold calibration.

int	A5256_Ch0Polarity
	Polarity of Ch0 in A5256 (POS, NEG)

int	GWn

uint32_t	GWaddr [20]
	Register Address.

uint32_t	GWdata [20]
	Data to write.

uint32_t	GWmask [20]
	Bit Mask.

Detailed Description

FERS configuration parameters structure (lib + board)

Definition at line 62 of file FERS_config.h.

Field Documentation

◆ bmutex

mutex_t bmutex

Definition at line 65 of file FERS_config.h.

◆ handle

int handle

Definition at line 69 of file FERS_config.h.

◆ OF_RawData

uint8_t OF_RawData

Enable saving raw data output files.

Definition at line 74 of file FERS_config.h.

◆ OF_LimitedSize

uint8_t OF_LimitedSize

Enable limited size on raw data output files.

Definition at line 75 of file FERS_config.h.

◆ MaxSizeDataOutputFile

float MaxSizeDataOutputFile

Maximum size writable for raw data output files in bytes. Minimum size allowed 1 MB.

Definition at line 76 of file FERS_config.h.

◆ OF_RawDataPath

char OF_RawDataPath[200]

Raw data files saving path.

Definition at line 77 of file FERS_config.h.

◆ AcquisitionMode

int AcquisitionMode

Acquisition mode (Spectroscopy, Timing, Counting, etc...). Options are board dependent.

Definition at line 82 of file FERS_config.h.

◆ StartRunMode

int StartRunMode

Start Mode (this is a HW setting that defines how to start/stop the acquisition in the boards)

Definition at line 83 of file FERS_config.h.

◆ StopRunMode

int StopRunMode

Stop Mode (for now, stop is always controlled by SW, but in the future it might be implemented in HW)

Definition at line 84 of file FERS_config.h.

◆ TestMode

uint32_t TestMode

Run with fixed data patterns generated by the FPGA.

Definition at line 85 of file FERS_config.h.

◆ TriggerMask

uint32_t TriggerMask

Bunch Trigger mask.

Definition at line 87 of file FERS_config.h.

◆ T0_outMask

uint32_t T0_outMask

T0-OUT mask.

Definition at line 88 of file FERS_config.h.

◆ T1_outMask

uint32_t T1_outMask

T1-OUT mask.

Definition at line 89 of file FERS_config.h.

◆ Tref_Mask

uint32_t Tref_Mask

Tref mask.

Definition at line 90 of file FERS_config.h.

◆ Veto_Mask

uint32_t Veto_Mask

Veto mask.

Definition at line 91 of file FERS_config.h.

◆ Validation_Mask

uint32_t Validation_Mask

Validation mask.

Definition at line 92 of file FERS_config.h.

◆ Validation_Mode

uint32_t Validation_Mode

Validation Mode: 0=disabled, 1=positive (accept), 2=negative (reject)

Definition at line 93 of file FERS_config.h.

◆ Counting_Mode

uint32_t Counting_Mode

Counting Mode (Singles, Paired_AND)

Definition at line 94 of file FERS_config.h.

◆ TrgIdMode

uint32_t TrgIdMode

Trigger ID: 0 = trigger counter, 1 = validation counter.

Definition at line 95 of file FERS_config.h.

◆ EnableServiceEvents

uint32_t EnableServiceEvents

Enable service events.

Definition at line 96 of file FERS_config.h.

◆ EnableCntZeroSuppr

uint32_t EnableCntZeroSuppr

Enable zero suppression in Counting Mode.

Definition at line 97 of file FERS_config.h.

◆ Dis_tdl

uint32_t Dis_tdl

Enable the TDL switching off when not used (DNIN: why is a parameter?)

Definition at line 98 of file FERS_config.h.

◆ EnableChannelTrgout

uint32_t EnableChannelTrgout

0 = Channel Trgout Disabled, 1 = Enabled (used in Citiroc only)

Definition at line 99 of file FERS_config.h.

◆ Enable_2nd_tstamp

uint32_t Enable_2nd_tstamp

Enable 2nd time stamp relative to the Tref signal.

Definition at line 100 of file FERS_config.h.

◆ EnableToT

uint32_t EnableToT

Enable readout of ToT (time over threshold) in A5202.

Definition at line 101 of file FERS_config.h.

◆ WaveformLength

uint32_t WaveformLength

Num of samples in the waveform.

Definition at line 102 of file FERS_config.h.

◆ WaveformSource

uint32_t WaveformSource

LG0, HG0, LG1, HG1 (High/Low Gain, chip 0/1)

Definition at line 103 of file FERS_config.h.

◆ Range_14bit

uint32_t Range_14bit

Use full 14 bit range for the A/D conversion.

Definition at line 104 of file FERS_config.h.

◆ En_Empty_Ev_Suppr

uint32_t En_Empty_Ev_Suppr

Enable event suppression (only in Custom header mode)

Definition at line 105 of file FERS_config.h.

◆ GateWidth

float GateWidth

Gate window width in ns (will be rounded to steps of 25 ns)

Definition at line 106 of file FERS_config.h.

◆ TrefWindow

float TrefWindow

Tref Windows in ns (Common start/stop)

Definition at line 107 of file FERS_config.h.

◆ TrefDelay

float TrefDelay

Tref delay in ns (can be negative)

Definition at line 108 of file FERS_config.h.

◆ PtrgPeriod

float PtrgPeriod

period in ns of the internal periodic trigger (dwell time)

Definition at line 109 of file FERS_config.h.

◆ TrgHoldOff

float TrgHoldOff

Retrigger protection time. Set the busy active for N clock cycles (0=disabled)

Definition at line 110 of file FERS_config.h.

◆ ChEnableMask

uint64_t ChEnableMask

Channel enable mask (64 ch)

Definition at line 115 of file FERS_config.h.

◆ ChEnableMask_e

uint64_t ChEnableMask_e

Channel enable mask of Mezzanine expansion (128 ch, A5203 only)

Definition at line 116 of file FERS_config.h.

◆ AnalogProbe

uint32_t AnalogProbe[2]

Analog probe in XROC ASICs (Preamp LG/HG, Slow Shaper HG/LG, Fast Shaper)

Definition at line 121 of file FERS_config.h.

◆ DigitalProbe

uint32_t DigitalProbe[2]

Digital probe in XROC ASICs (peak Sens HG/LG) or FPGA (start_conv, data_commit...)

Definition at line 122 of file FERS_config.h.

◆ ProbeChannel

uint32_t ProbeChannel[2]

Channel to probe.

Definition at line 123 of file FERS_config.h.

◆ FiberDelayAdjust

float FiberDelayAdjust[4][8][16]

Fiber length (in meters) for individual tuning of the propagation delay along the TDL daisy chains.

Definition at line 128 of file FERS_config.h.

◆ TdlClkPhase

uint32_t TdlClkPhase

Recovered clock phase shift: 0=0, 1=90, 2=180, 3=270.

Definition at line 129 of file FERS_config.h.

◆ MaxPck_Block

uint32_t MaxPck_Block

Max. number of packets (events) that the concentrator can aggregate in one Data Block (0 = use default in FW)

Definition at line 130 of file FERS_config.h.

◆ MaxPck_Train

uint32_t MaxPck_Train

Max. number of packets (events) that the FERS unit can transmit to the concentrator in a single data train (0 = use default in FW)

Definition at line 131 of file FERS_config.h.

◆ CncBufferSize

uint32_t CncBufferSize

Data buffer size (in 32 bit words) in the concentrator; stop trains when this level is reached (0 = use default in FW)

Definition at line 132 of file FERS_config.h.

◆ CncProbe_A

uint32_t CncProbe_A

Digital Probe in the concentrator (output FA)

Definition at line 133 of file FERS_config.h.

◆ CncProbe_B

uint32_t CncProbe_B

Digital Probe in the concentrator (output FB)

Definition at line 134 of file FERS_config.h.

◆ Tlogic_Mask

uint64_t Tlogic_Mask

Trigger Logic enable mask.

Definition at line 139 of file FERS_config.h.

◆ TriggerLogic

uint32_t TriggerLogic

Trigger Logic Definition.

Definition at line 140 of file FERS_config.h.

◆ MajorityLevel

uint32_t MajorityLevel

Majority Level.

Definition at line 141 of file FERS_config.h.

◆ ChTrg_Width

float ChTrg_Width

Self Trg Width in ns => Coinc windows for paired counting and trigger logic.

Definition at line 142 of file FERS_config.h.

◆ Tlogic_Width

float Tlogic_Width

TriggerLogic output width (0=linear)

Definition at line 143 of file FERS_config.h.

◆ ZS_Threshold_LG

uint16_t ZS_Threshold_LG[64]

Low Threshold for zero suppression (LG)

Definition at line 148 of file FERS_config.h.

◆ ZS_Threshold_HG

uint16_t ZS_Threshold_HG[64]

Low Threshold for zero suppression (HG)

Definition at line 149 of file FERS_config.h.

◆ QD_FineThreshold

uint16_t QD_FineThreshold[64]

Fine Threshold for Citiroc charge discriminator.

Definition at line 150 of file FERS_config.h.

◆ TD_FineThreshold

uint16_t TD_FineThreshold[64]

Fine Threshold for Citiroc time discriminator.

Definition at line 151 of file FERS_config.h.

◆ HG_Gain

uint16_t HG_Gain[64]

Gain of the High Gain Preamp.

Definition at line 152 of file FERS_config.h.

◆ LG_Gain

uint16_t LG_Gain[64]

Gain of the Low Gain Preamp.

Definition at line 153 of file FERS_config.h.

◆ PAQ_Gain

uint16_t PAQ_Gain[64]

Gain of the Charge Preamp (Psiroc)

Definition at line 154 of file FERS_config.h.

◆ PAQ_Comp

uint16_t PAQ_Comp[64]

Gain of the Charge Preamp (Psiroc)

Definition at line 155 of file FERS_config.h.

◆ HV_IndivAdj

uint16_t HV_IndivAdj[64]

HV individual bias adjust (Citiroc 8bit input DAC)

Definition at line 156 of file FERS_config.h.

◆ InputPolarity

uint16_t InputPolarity[64]

Preamp Input Polarity.

Definition at line 157 of file FERS_config.h.

◆ QD_Mask

uint64_t QD_Mask

Enable mask of Charge Discriminator.

Definition at line 158 of file FERS_config.h.

◆ TD1_Mask

uint64_t TD1_Mask

Enable mask of Time Discriminator 1.

Definition at line 159 of file FERS_config.h.

◆ TD2_Mask

uint64_t TD2_Mask

Enable mask of Time Discriminator 2.

Definition at line 160 of file FERS_config.h.

◆ TD_Mask

uint64_t TD_Mask

Enable mask of Fast Shaper Discriminator (Psiroc)

Definition at line 161 of file FERS_config.h.

◆ TOTD_Mask

uint64_t TOTD_Mask

Enable mask of TOT Discriminator (Psiroc)

Definition at line 162 of file FERS_config.h.

◆ TD_CoarseThreshold

uint32_t TD_CoarseThreshold

Coarse Threshold for Citiroc time discriminator.

Definition at line 163 of file FERS_config.h.

◆ HG_ShapingTime

uint32_t HG_ShapingTime

Shaping Time of the High Gain preamp.

Definition at line 164 of file FERS_config.h.

◆ LG_ShapingTime

uint32_t LG_ShapingTime

Shaping Time of the Low Gain preamp.

Definition at line 165 of file FERS_config.h.

◆ Enable_HV_Adjust

uint32_t Enable_HV_Adjust

Enable input DAC for HV fine adjust.

Definition at line 166 of file FERS_config.h.

◆ HV_Adjust_Range

uint16_t HV_Adjust_Range

HV adj DAC range (reference): 0 = 2.5V, 1 = 4.5V, ?=DISABLED.

Definition at line 167 of file FERS_config.h.

◆ T_Gain

uint16_t T_Gain[64]

T-Preamp gain.

Definition at line 168 of file FERS_config.h.

◆ TD1_CoarseThreshold

uint16_t TD1_CoarseThreshold

Coarse Threshold for Time discriminator 1.

Definition at line 169 of file FERS_config.h.

◆ TD2_CoarseThreshold

uint16_t TD2_CoarseThreshold

Coarse Threshold for Time discriminator 2.

Definition at line 170 of file FERS_config.h.

◆ TOTD_CoarseThreshold

uint16_t TOTD_CoarseThreshold

Coarse Threshold for TOT discriminator.

Definition at line 171 of file FERS_config.h.

◆ QD_CoarseThreshold

uint16_t QD_CoarseThreshold

Coarse Threshold for Charge discriminator.

Definition at line 172 of file FERS_config.h.

◆ TD1_FineThreshold

uint16_t TD1_FineThreshold[64]

Fine Threshold for Time discriminator 1.

Definition at line 173 of file FERS_config.h.

◆ TD2_FineThreshold

uint16_t TD2_FineThreshold[64]

Fine Threshold for Time discriminator 2.

Definition at line 174 of file FERS_config.h.

◆ TOTD_FineThreshold

uint16_t TOTD_FineThreshold[64]

Fine Threshold for TOT discriminator.

Definition at line 175 of file FERS_config.h.

◆ HG_ShapingTime_ind

uint16_t HG_ShapingTime_ind[64]

Shaping Time of the High Gain preamp (individual)

Definition at line 176 of file FERS_config.h.

◆ LG_ShapingTime_ind

uint16_t LG_ShapingTime_ind[64]

Shaping Time of the Low Gain preamp (individual)

Definition at line 177 of file FERS_config.h.

◆ PeakDetectorMode

uint32_t PeakDetectorMode

Peaking Mode: 0 = Peak Stretcher, 1 = Track&Hold.

Definition at line 178 of file FERS_config.h.

◆ EnableQdiscrLatch

uint32_t EnableQdiscrLatch

Q-dicr mode: 1 = Latched, 0 = Direct.

Definition at line 179 of file FERS_config.h.

◆ FastShaperInput

uint32_t FastShaperInput

Fast Shaper (Tdiscr) connection: 0 = High Gain PA, 1 = Low Gain PA.

Definition at line 180 of file FERS_config.h.

◆ TestPulsePreamp

uint32_t TestPulsePreamp

1=LG, 2=HG, 3=BOTH

Definition at line 181 of file FERS_config.h.

◆ TestPulseDestination

int TestPulseDestination

-1=ALL, -2=EVEN, -3=ODD or channel number (0 to 63) for single channel pulsing

Definition at line 182 of file FERS_config.h.

◆ CitirocCfgMode

uint32_t CitirocCfgMode

0=from regs, 1=from file

Definition at line 183 of file FERS_config.h.

◆ HoldDelay

float HoldDelay

Time between Trigger and Hold.

Definition at line 184 of file FERS_config.h.

◆ MuxClkPeriod

float MuxClkPeriod

Period of the Mux Clock.

Definition at line 185 of file FERS_config.h.

◆ MuxNSmean

uint32_t MuxNSmean

Num of samples for the Mux mean: 0: 4 samples, 1: 16 samples.

Definition at line 186 of file FERS_config.h.

◆ GainSelect

uint32_t GainSelect

Select gain between High/Low/Auto.

Definition at line 187 of file FERS_config.h.

◆ Pedestal

uint16_t Pedestal

Common pedestal added to all channels.

Definition at line 188 of file FERS_config.h.

◆ TestPulseSource

int TestPulseSource

EXT, INT_T0, INT_T1, INT_PTRG, INT_SW.

Definition at line 193 of file FERS_config.h.

◆ TestPulseAmplitude

uint32_t TestPulseAmplitude

DAC setting for the internal test pulser (12 bit). Meaningless for TestPulseSource=EXT.

Definition at line 194 of file FERS_config.h.

◆ HV_Vbias

float HV_Vbias

Voltage setting for HV.

Definition at line 200 of file FERS_config.h.

◆ HV_Imax

float HV_Imax

Imax for HV.

Definition at line 201 of file FERS_config.h.

◆ TempSensCoeff

float TempSensCoeff[3]

Temperature Sensor Coefficients (2=quad, 1=lin, 0=offset)

Definition at line 202 of file FERS_config.h.

◆ TempFeedbackCoeff

float TempFeedbackCoeff

Temperature Feedback Coeff: Vout = Vset - k * (T-25)

Definition at line 203 of file FERS_config.h.

◆ EnableTempFeedback

int EnableTempFeedback

Enable Temp Feedback.

Definition at line 204 of file FERS_config.h.

◆ MeasMode

uint32_t MeasMode

LEAD_ONLY, LEAD_TRAIL, LEAD_TOT8, LEAD_TOT11.

Definition at line 210 of file FERS_config.h.

◆ En_Head_Trail

uint32_t En_Head_Trail

Enable Header and Trailer: 0=Keep all (group header+trail), 1=One word, 2=Header and trailer suppressed.

Definition at line 211 of file FERS_config.h.

◆ HighResClock

uint32_t HighResClock

High Res clock distribution (MCX connectors)

Definition at line 212 of file FERS_config.h.

◆ GlitchFilterDelay

uint32_t GlitchFilterDelay

Delay of the glitch filter (~800 ps to ~10 ns with 16 steps)

Definition at line 213 of file FERS_config.h.

◆ GlitchFilterMode

uint32_t GlitchFilterMode

DISABLED, TRAILING, LEADING, BOTH.

Definition at line 214 of file FERS_config.h.

◆ TDC_ChBufferSize

uint32_t TDC_ChBufferSize

Channel buffer size in the picoTDC (set a limit to the max number of hits acquired by the channel)

Definition at line 215 of file FERS_config.h.

◆ TriggerBufferSize

uint32_t TriggerBufferSize

Size of the trigger buffer in the FPGA (limits the number or pending triggers, already sent to the TDC but not written in the output FIFO yet)

Definition at line 216 of file FERS_config.h.

◆ HeaderField0

uint32_t HeaderField0

Header Field0 (for test only, default=4=near full flags (ch 0..7 of the port) - 00000CCCCCCCC)

Definition at line 217 of file FERS_config.h.

◆ HeaderField1

uint32_t HeaderField1

Header Field1 (for test only, default=5=near full flags (ch 8..15 of the port + RO_buff, TrgBuff) - RT000CCCCCCCC)

Definition at line 218 of file FERS_config.h.

◆ LeadTrail_LSB

uint32_t LeadTrail_LSB

Leading/Trailing LSB required by the user: 0: LSB = ~3ps, N: LSB = 3ps * 2^N, (Max N=10; LSB = ~3.125 ns)

Definition at line 219 of file FERS_config.h.

◆ ToT_LSB

uint32_t ToT_LSB

ToT LSB required by the user: 0: LSB = 3.125ps, N: LSB = 3.125ps * 2^N, (Max N=18; LSB = ~800 ns)

Definition at line 220 of file FERS_config.h.

◆ ToT_reject_low_thr

uint16_t ToT_reject_low_thr

The FPGA suppresses the Hits with ToT > low_threshold (0 disabled)

Definition at line 221 of file FERS_config.h.

◆ ToT_reject_high_thr

uint16_t ToT_reject_high_thr

The FPGA suppresses the Hits with ToT < high_threshold (0 disabled)

Definition at line 222 of file FERS_config.h.

◆ TrgWindowWidth

float TrgWindowWidth

Trigger window width in ns (will be rounded to steps of 25 ns)

Definition at line 223 of file FERS_config.h.

◆ TrgWindowOffset

float TrgWindowOffset

Trigger window offset in ns; can be negative (will be rounded to steps of 25 ns)

Definition at line 224 of file FERS_config.h.

◆ TDCpulser_Width

float TDCpulser_Width

picoTDC Pulser Output (width in ns)

Definition at line 226 of file FERS_config.h.

◆ TDCpulser_Period

float TDCpulser_Period

picoTDC Pulser Output (period in ns)

Definition at line 227 of file FERS_config.h.

◆ Ch_Offset

uint32_t Ch_Offset[128]

Channel Offset.

Definition at line 228 of file FERS_config.h.

◆ AdapterType

int AdapterType

Definition at line 235 of file FERS_config.h.

◆ DiscrThreshold

float DiscrThreshold[128]

Discriminator Threshold.

Definition at line 236 of file FERS_config.h.

◆ DiscrThreshold2

float DiscrThreshold2[128]

Discriminator 2nd Threshold (double thershold mode only)

Definition at line 237 of file FERS_config.h.

◆ DisableThresholdCalib

int DisableThresholdCalib

Disable threshold calibration.

Definition at line 238 of file FERS_config.h.

◆ A5256_Ch0Polarity

int A5256_Ch0Polarity

Polarity of Ch0 in A5256 (POS, NEG)

Definition at line 239 of file FERS_config.h.

◆ GWn

int GWn

Definition at line 245 of file FERS_config.h.

◆ GWaddr

uint32_t GWaddr[20]

Register Address.

Definition at line 246 of file FERS_config.h.

◆ GWdata

uint32_t GWdata[20]

Data to write.

Definition at line 247 of file FERS_config.h.

◆ GWmask

uint32_t GWmask[20]

Bit Mask.

Definition at line 248 of file FERS_config.h.

The documentation for this struct was generated from the following file:

FERS_config.h

Data Fields