Clock and TDL delay definitions. More...

Collaboration diagram for Clock definition:

Macros
#define	TDL_COMMAND_DELAY 1000000

#define	CLK_PERIOD_5202 8

#define	CLK_PERIOD_5203 12.8

#define	CLK_PERIOD_5204 12.8

Detailed Description

Clock and TDL delay definitions.

Macro Definition Documentation

◆ TDL_COMMAND_DELAY

#define TDL_COMMAND_DELAY 1000000

Delay for the command execution in TDlink (the delay must be greater than the maximum delivery time of the command acress the TDL chains). 1 LSB = 10 ns

Definition at line 295 of file FERSlib.h.

◆ CLK_PERIOD_5202

#define CLK_PERIOD_5202 8

FPGA clock period in ns (5202)

Definition at line 296 of file FERSlib.h.

◆ CLK_PERIOD_5203

#define CLK_PERIOD_5203 12.8

FPGA clock period in ns (5203)

Definition at line 297 of file FERSlib.h.

◆ CLK_PERIOD_5204

#define CLK_PERIOD_5204 12.8

FPGA clock period in ns (5204)