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Data Structures
struct	XR_Cfg_t

struct	picoTDC_Cfg_t

Macros
#define	_REGISTERS_H

#define	INDIV_ADDR(addr, ch)

#define	BCAST_ADDR(addr)

#define	STATUS_READY (1 << 0)

#define	STATUS_FAIL (1 << 1)

#define	STATUS_RUNNING (1 << 2)

#define	STATUS_TDL_SYNC (1 << 3)

#define	STATUS_FPGA_OVERTEMP (1 << 4)

#define	STATUS_TDC_RO_ERR (1 << 5)

#define	STATUS_TDLINK_LOL (1 << 6)

#define	STATUS_TDC0_LOL (1 << 7)

#define	STATUS_TDC1_LOL (1 << 8)

#define	STATUS_RO_CLK_LOL (1 << 9)

#define	STATUS_TDL_DISABLED (1 << 10)

#define	STATUS_TDC0_OVERTEMP (1 << 11)

#define	STATUS_TDC1_OVERTEMP (1 << 12)

#define	STATUS_BOARD_OVERTEMP (1 << 13)

#define	STATUS_CRC_ERROR (1 << 14)

#define	STATUS_UNUSED_15 (1 << 15)

#define	STATUS_SPI_BUSY (1 << 16)

#define	STATUS_I2C_BUSY (1 << 17)

#define	STATUS_I2C_FAIL (1 << 18)

#define	crcfg_qdiscr_latch 0
	Qdiscr output: 0=latched, 1=direct (bit 258 of SR)

#define	crcfg_sca_bias 1
	SCA bias: 0=high (5MHz readout speed), 1=weak (bit 301 of SR)

#define	crcfg_pdet_mode_hg 2
	Peak_det mode HighGain: 0=peak detector, 1=T&H (bit 306 of SR)

#define	crcfg_pdet_mode_lg 3
	Peak_det mode LowGain: 0=peak detector, 1=T&H (bit 307 of SR)

#define	crcfg_ps_ctrl_logic 4
	Peak Sens Ctrl Logic: 0=internal, 1=external=PS_modeb_ext (bit 308 of SR)

#define	crcfg_ps_trg_source 5
	Peak Sens Trg source: 0=internal, 1=external (bit 309 of SR)

#define	crcfg_lg_pa_bias 6
	LG Preamp bias: 0=normal, 1=weak (bit 323 of SR)

#define	crcfg_pa_fast_sh 7
	Fast shaper connection: 0=high gain pa, 1=low gain pa (bit 328 of SR)

#define	crcfg_8bit_dac_ref 8
	HV adjust DAC reference: 0=2.5V, 1=4.5V (bit 330 of SR)

#define	crcfg_ota_bias 9
	Output OTA buffer bias auto off: 0=auto, 1=force on (bit 1133 of SR)

#define	crcfg_trg_polarity 10
	Trigger polarity: 0=pos, 1=neg (bit 1141 of SR)

#define	crcfg_enable_chtrg 11
	Enable channel triggers (bit 1143 of SR)

#define	crcfg_enable_gtrg 16
	Enable propagation of gtrg to the Citiroc pin global_trig.

#define	crcfg_enable_veto 17
	Enable propagation of gate (= not veto) to the Citiroc pin val_evt.

#define	crcfg_repeat_raz 18
	Enable loop asserting raz_chn until nor_charge stays active.

#define	SHAPING_TIME_12_5NS 6

#define	SHAPING_TIME_25NS 5

#define	SHAPING_TIME_37_5NS 4

#define	SHAPING_TIME_50NS 3

#define	SHAPING_TIME_62_5NS 2

#define	SHAPING_TIME_75NS 1

#define	SHAPING_TIME_87_5NS 0

#define	TEST_PULSE_SOURCE_EXT 0

#define	TEST_PULSE_SOURCE_T0_IN 1

#define	TEST_PULSE_SOURCE_T1_IN 2

#define	TEST_PULSE_SOURCE_PTRG 3

#define	TEST_PULSE_SOURCE_SW_CMD 4

#define	TEST_PULSE_PREAMP_LG 1

#define	TEST_PULSE_PREAMP_HG 2

#define	TEST_PULSE_PREAMP_BOTH 3

#define	TEST_PULSE_DEST_ALL 1

#define	TEST_PULSE_DEST_EVEN 2

#define	TEST_PULSE_DEST_ODD 3

#define	TEST_PULSE_DEST_NONE 4

#define	DPROBE_OFF 0

#define	DPROBE_PEAK_LG 1

#define	DPROBE_PEAK_HG 2

#define	DPROBE_HOLD 3

#define	DPROBE_START_CONV 4

#define	DPROBE_DATA_COMMIT 5

#define	DPROBE_DATA_VALID 6

#define	DPROBE_CLK_1024 7

#define	DPROBE_VAL_WINDOW 8

#define	DPROBE_T_OR 9

#define	DPROBE_Q_OR 10

#define	DPROBE_XROC_TRG 11

#define	GAIN_SEL_AUTO 0

#define	GAIN_SEL_HIGH 1

#define	GAIN_SEL_LOW 2

#define	GAIN_SEL_BOTH 3

#define	FAST_SHAPER_INPUT_HGPA 0

#define	FAST_SHAPER_INPUT_LGPA 1

#define	a_XR_ChControl(i)
	Channel Settings (XROC channels are swapped on PCB => ch0 goes in ch63...)

#define	a_XR_ASIC_bias 0x0040
	ASIC biasing.

#define	a_XR_common_cfg 0x0041
	Common settings.

#define	a_XR_out_cfg 0x0042
	Output settings.

#define	a_XR_event_val 0x0043
	Event validation gating.

#define	a_pTDC_Control 0x0004
	R/W - Magic word + reset bits.

#define	a_pTDC_Enable 0x0008
	R/W - Enable bits.

#define	a_pTDC_Header 0x000C
	R/W - Event data format (header)

#define	a_pTDC_TrgWindow 0x0010
	R/W - Trg Window Latency + Width.

#define	a_pTDC_Trg0Del_ToT 0x0014
	R/W - Trg_Ch0 Delay + ToT.

#define	a_pTDC_BunchCount 0x0018
	R/W - Bunch Count Overflow + Offset.

#define	a_pTDC_EventID 0x001C
	R/W - EventID.

#define	a_pTDC_Ch_Control(i)
	R/W - Channel offset + some Ctrl bits.

#define	a_pTDC_Buffers 0x0120
	R/W - Buffer settings.

#define	a_pTDC_Hit_RX_TX 0x0124
	R/W - Hit RX/TX.

#define	a_pTDC_DLL_TG 0x0128
	R/W - DLL/TG.

#define	a_pTDC_PLL1 0x0130
	R/W - PLL1.

#define	a_pTDC_PLL2 0x0134
	R/W - PLL2.

#define	a_pTDC_Clocks 0x0138

#define	a_pTDC_ClockShift 0x013C

#define	a_pTDC_Hit_RXen_T 0x0140

#define	a_pTDC_Hit_RXen_B 0x0144

#define	a_pTDC_PulseGen1 0x0148

#define	a_pTDC_PulseGen2 0x014C

#define	a_pTDC_PulseGen3 0x0150

#define	a_pTDC_ErrorFlagCtrl 0x0154

#define	a_pTDC_Ch_Status(i)

#define	a_pTDC_Trg_Status(i)

#define	a_pTDC_RO_Status(i)

#define	a_pTDC_Cfg_Parity(i)

#define	a_pTDC_PLL_Caps 0x28C

#define	a_pTDC_DelayAdjust 0xFFFC

#define	I2C_ADDR_TDC(i)

#define	I2C_ADDR_PLL0 0x68

#define	I2C_ADDR_PLL1 0x69

#define	I2C_ADDR_PLL2 0x70

#define	I2C_ADDR_EEPROM_MEM 0x57

#define	I2C_ADDR_XR 0x78


#define	a_acq_ctrl 0x01000000
	FERS configuration registers.

#define	a_run_mask 0x01000004
	Run mask: bit[0]=SW, bit[1]=T0-IN.

#define	a_trg_mask 0x01000008
	Global trigger mask: bit[0]=SW, bit[1]=T1-IN, bit[2]=Q-OR, bit[3]=Maj, bit[4]=Periodic.

#define	a_tref_mask 0x0100000C
	Tref mask: bit[0]=T0-IN, bit[1]=T1-IN, bit[2]=Q-OR, bit[3]=T-OR, bit[5]=Periodic.

#define	a_t0_out_mask 0x01000014
	T0 out mask.

#define	a_t1_out_mask 0x01000018
	T1 out mask.

#define	a_veto_mask 0x0100001C
	Veto mask: bit[0]=Cmd from TDL, bit[1]=T0-IN, bit[2]=T1-IN,.

#define	a_tref_delay 0x01000048
	Delay of the time reference for the coincidences.

#define	a_tref_window 0x0100004C
	Tref coincidence window (for list mode)

#define	a_dwell_time 0x01000050
	Dwell time (periodic trigger) in clk cyclces. 0 => OFF.

#define	a_list_size 0x01000054
	Number of 32 bit words in a packet in timing mode (list mode)

#define	a_pck_maxcnt 0x01000064
	Max num of packets transmitted to the TDL.

#define	a_channel_mask_0 0x01000100
	Input Channel Mask (ch 0 to 31)

#define	a_channel_mask_1 0x01000104
	Input Channel Mask (ch 32 to 63)

#define	a_fw_rev 0x01000300
	Firmware Revision.

#define	a_acq_status 0x01000304
	Acquisition Status.

#define	a_real_time 0x01000308
	Real Time in ms.

#define	a_dead_time 0x01000310
	Dead Time in ms.

#define	a_board_temp 0x01000340
	Board Temp.

#define	a_fpga_temp 0x01000348
	FPGA die Temperature.

#define	a_pid 0x01000400
	PID.

#define	a_pcb_rev 0x01000404
	PCB revision.

#define	a_fers_code 0x01000408
	Fers CODE (5202)

#define	a_rebootfpga 0x0100FFF0
	reboot FPGA from FW uploader

#define	a_test_led 0x01000228
	LED test mode.

#define	a_tdc_mode 0x0100022C
	TDC Mode.

#define	a_tdc_data 0x01000230
	TDC Data.

#define	a_sw_compatib 0x01004000
	SW compatibility.

#define	a_commands 0x01008000
	Send Commands (for Eth and USB)

#define	a_validation_mask 0x01000010
	Validation mask: bit[0]=Cmd from TDL, bit[1]=T0-IN, bit[2]=T1-IN.

#define	a_acq_ctrl2 0x01000020
	Acquisition Control Register 2.

#define	a_dprobe_5202 0x01000068
	Digital probes (signal inspector)

#define	a_citiroc_cfg 0x01000108
	Citiroc common configuration bits.

#define	a_citiroc_en 0x0100010C
	Citiroc internal parts enable mask.

#define	a_citiroc_probe 0x01000110
	Citiroc probes (signal inspector)

#define	a_qd_coarse_thr 0x01000114
	Coarse threshold for the Citiroc Qdiscr (10 bit DAC)

#define	a_td_coarse_thr 0x01000118
	Coarse threshold for the Citiroc Tdiscr (10 bit DAC)

#define	a_lg_sh_time 0x0100011C
	Low gain shaper time constant.

#define	a_hg_sh_time 0x01000120
	High gain shaper time constant.

#define	a_hold_delay 0x01000124
	Time from gtrg to peak hold.

#define	a_amux_seq_ctrl 0x01000128
	Timing parameters for the analog mux readout and conversion.

#define	a_wave_length 0x0100012C
	Waveform Length.

#define	a_scbs_ctrl 0x01000130
	Citiroc SC bit stream index and select.

#define	a_scbs_data 0x01000134
	Citiroc SC bit stream data.

#define	a_qdiscr_mask_0 0x01000138
	Charge Discriminator mask.

#define	a_qdiscr_mask_1 0x0100013C
	Charge Discriminator mask.

#define	a_tdiscr_mask_0 0x01000140
	Time Discriminator mask.

#define	a_tdiscr_mask_1 0x01000144
	Time Discriminator mask.

#define	a_tpulse_ctrl 0x01000200
	Test pulse mask.

#define	a_tpulse_dac 0x01000204
	Internal Test Pulse amplitude.

#define	a_hv_regaddr 0x01000210
	HV Register Address and Data Type.

#define	a_hv_regdata 0x01000214
	HV Register Data.

#define	a_trgho 0x01000218
	Trigger Hold off.

#define	a_dc_offset 0x01000220
	DAC for DC offset.

#define	a_spi_data 0x01000224
	SPI R/W data (for Flash Memory access)

#define	a_test_led 0x01000228
	LED test mode.

#define	a_tdc_mode 0x0100022C
	TDC Mode.

#define	a_tdc_data 0x01000230
	TDC Data.

#define	a_tlogic_def 0x01000234
	Trigger Logic Definition.

#define	a_tlogic_width 0x0100023C
	Monostable for Trigger logic output.

#define	a_hit_width 0x01000238
	Monostable for CR triggers.

#define	a_i2c_addr_5202 0x01000240
	I2C Addr.

#define	a_i2c_data_5202 0x01000244
	I2C Data.

#define	a_t_or_cnt 0x01000350
	T-OR counter.

#define	a_q_or_cnt 0x01000354
	Q-OR counter.

#define	a_hv_Vmon 0x01000356
	HV Vmon.

#define	a_hv_Imon 0x01000358
	HV Imon.

#define	a_hv_status 0x01000360
	HV Status.

#define	a_uC_status 0x01000600
	uC status

#define	a_uC_shutdown 0x01000604
	uC shutdown

#define	a_zs_lgthr 0x02000000
	Threshold for zero suppression (LG)

#define	a_zs_hgthr 0x02000004
	Threshold for zero suppression (HG)

#define	a_qd_fine_thr 0x02000008
	Fine individual threshold for the Citiroc Qdiscr (4 bit DAC)

#define	a_td_fine_thr 0x0200000C
	Fine individual threshold for the Citiroc Tdiscr (4 bit DAC)

#define	a_lg_gain 0x02000010
	Preamp Low Gain Setting.

#define	a_hg_gain 0x02000014
	Preamp High Gain Setting.

#define	a_hv_adj 0x02000018
	HV individual adjust (8 bit DAC)

#define	a_hitcnt 0x02000800
	Hit counters.

#define	a_io_ctrl 0x01000020
	I/O control.

#define	a_trg_delay 0x01000060
	Trigger delay.

#define	a_dprobe_5203 0x01000110
	Digital probe selection.

#define	a_lsof_almfull_bsy 0x01000068
	Almost Full level of LSOF (Event Data FIFO) to assert Busy.

#define	a_lsof_almfull_skp 0x0100006C
	Almost Full level of LSOF (Event Data FIFO) to skip data.

#define	a_trgf_almfull 0x01000070
	Almost Full level of Trigger FIFO.

#define	a_tot_rej_lthr 0x01000074
	ToT Reject Lower Threshold (0=disabled)

#define	a_tot_rej_hthr 0x01000078
	ToT Reject Higer Threshold (0=disabled)

#define	a_trg_hold_off 0x0100007A
	Retrigger protection time. Set the busy active for N clock cycles (0=disabled)

#define	a_strm_ptrg 0x0100007C
	Periodic trigger for streaming mode.

#define	a_i2c_addr_5203 0x01000200
	I2C Addr.

#define	a_i2c_data_5203 0x01000204
	I2C Data.

#define	a_trg_cnt 0x01000318
	Trigger counter.

#define	a_tdcro_status 0x0100031A
	TDC readout Status.

#define	a_rej_trg_cnt 0x0100031C
	Rejected Trigger counter.

#define	a_zs_trg_cnt 0x01000320
	Zero Suppressed Trigger counter.

#define	a_clk_out_phase 0x01000330
	Phase between TDC clock and FPGA clock (0x0000 = 0 deg; 0xFFFF = 180 deg)

#define	a_tdc0_temp 0x01000354
	TDC0 Temperature.

#define	a_tdc1_temp 0x01000358
	TDC1 Temperature.

#define	a_spi_data 0x01000224
	SPI R/W data (for Flash Memory access)

#define	a_tlogic_mask_0 0x01000140
	Trigger FPGA-Tlogic mask (in A5202 it corresponds to a_tdiscr_mask_0)

#define	a_tlogic_mask_1 0x01000144
	Trigger FPGA-Tlogic mask (in A5202 it corresponds to a_tdiscr_mask_1)


#define	CMD_TIME_RESET 0x11
	FERS board commands.

#define	CMD_ACQ_START 0x12
	Start acquisition.

#define	CMD_ACQ_STOP 0x13
	Stop acquisition.

#define	CMD_TRG 0x14
	Send software trigger.

#define	CMD_RESET 0x15
	Global Reset (clear data, set all regs to default)

#define	CMD_TPULSE 0x16
	Send a test pulse.

#define	CMD_RES_PTRG 0x17
	Reset periodic trigger counter (and rearm PTRG in single pulse mode)

#define	CMD_CLEAR 0x18
	Clear Data.

#define	CMD_VALIDATION 0x19
	Trigger Validation (either positive = accept or negative = reject)

#define	CMD_SET_VETO 0x1A
	Set Veto.

#define	CMD_CLEAR_VETO 0x1B
	Clear Veto.

#define	CMD_TDL_SYNC 0x1C
	Sync signal from TDL.

#define	CMD_USE_ICLK 0x1E
	Use internal CLK for FPGA.

#define	CMD_USE_ECLK 0x1F
	Use external CLK for FPGA.

#define	CMD_CFG_ASIC 0x20
	Configure ASIC (load shift register). If used, refer to FERS_configure_5202.c, at.

Macro Definition Documentation

◆ _REGISTERS_H

#define _REGISTERS_H

CAEN SpA - Front End Division Via Vetraia, 11 - 55049 - Viareggio ITALY +390594388398 - www.caen.it

Note: TERMS OF USE: This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. The user relies on the software, documentation and results solely at his own risk.

Definition at line 18 of file FERS_Registers_520X.h.

◆ INDIV_ADDR

#define INDIV_ADDR	(		addr,
			ch )

Value:

(0x02000000 | ((addr) & 0xFFFF) | ((ch)<<16))

Definition at line 29 of file FERS_Registers_520X.h.

◆ BCAST_ADDR

#define BCAST_ADDR ( addr )

Value:

(0x03000000 | ((addr) & 0xFFFF))

Definition at line 30 of file FERS_Registers_520X.h.

◆ STATUS_READY

#define STATUS_READY (1 << 0)

Definition at line 160 of file FERS_Registers_520X.h.

◆ STATUS_FAIL

#define STATUS_FAIL (1 << 1)

Definition at line 161 of file FERS_Registers_520X.h.

◆ STATUS_RUNNING

#define STATUS_RUNNING (1 << 2)

Definition at line 162 of file FERS_Registers_520X.h.

◆ STATUS_TDL_SYNC

#define STATUS_TDL_SYNC (1 << 3)

Definition at line 163 of file FERS_Registers_520X.h.

◆ STATUS_FPGA_OVERTEMP

#define STATUS_FPGA_OVERTEMP (1 << 4)

Definition at line 164 of file FERS_Registers_520X.h.

◆ STATUS_TDC_RO_ERR

#define STATUS_TDC_RO_ERR (1 << 5)

Definition at line 165 of file FERS_Registers_520X.h.

◆ STATUS_TDLINK_LOL

#define STATUS_TDLINK_LOL (1 << 6)

Definition at line 166 of file FERS_Registers_520X.h.

◆ STATUS_TDC0_LOL

#define STATUS_TDC0_LOL (1 << 7)

Definition at line 167 of file FERS_Registers_520X.h.

◆ STATUS_TDC1_LOL

#define STATUS_TDC1_LOL (1 << 8)

Definition at line 168 of file FERS_Registers_520X.h.

◆ STATUS_RO_CLK_LOL

#define STATUS_RO_CLK_LOL (1 << 9)

Definition at line 169 of file FERS_Registers_520X.h.

◆ STATUS_TDL_DISABLED

#define STATUS_TDL_DISABLED (1 << 10)

Definition at line 170 of file FERS_Registers_520X.h.

◆ STATUS_TDC0_OVERTEMP

#define STATUS_TDC0_OVERTEMP (1 << 11)

Definition at line 171 of file FERS_Registers_520X.h.

◆ STATUS_TDC1_OVERTEMP

#define STATUS_TDC1_OVERTEMP (1 << 12)

Definition at line 172 of file FERS_Registers_520X.h.

◆ STATUS_BOARD_OVERTEMP

#define STATUS_BOARD_OVERTEMP (1 << 13)

Definition at line 173 of file FERS_Registers_520X.h.

◆ STATUS_CRC_ERROR

#define STATUS_CRC_ERROR (1 << 14)

Definition at line 174 of file FERS_Registers_520X.h.

◆ STATUS_UNUSED_15

#define STATUS_UNUSED_15 (1 << 15)

Definition at line 175 of file FERS_Registers_520X.h.

◆ STATUS_SPI_BUSY

#define STATUS_SPI_BUSY (1 << 16)

Definition at line 176 of file FERS_Registers_520X.h.

◆ STATUS_I2C_BUSY

#define STATUS_I2C_BUSY (1 << 17)

Definition at line 177 of file FERS_Registers_520X.h.

◆ STATUS_I2C_FAIL

#define STATUS_I2C_FAIL (1 << 18)

Definition at line 178 of file FERS_Registers_520X.h.

◆ crcfg_qdiscr_latch

#define crcfg_qdiscr_latch 0

Qdiscr output: 0=latched, 1=direct (bit 258 of SR)

Definition at line 210 of file FERS_Registers_520X.h.

◆ crcfg_sca_bias

#define crcfg_sca_bias 1

SCA bias: 0=high (5MHz readout speed), 1=weak (bit 301 of SR)

Definition at line 211 of file FERS_Registers_520X.h.

◆ crcfg_pdet_mode_hg

#define crcfg_pdet_mode_hg 2

Peak_det mode HighGain: 0=peak detector, 1=T&H (bit 306 of SR)

Definition at line 212 of file FERS_Registers_520X.h.

◆ crcfg_pdet_mode_lg

#define crcfg_pdet_mode_lg 3

Peak_det mode LowGain: 0=peak detector, 1=T&H (bit 307 of SR)

Definition at line 213 of file FERS_Registers_520X.h.

◆ crcfg_ps_ctrl_logic

#define crcfg_ps_ctrl_logic 4

Peak Sens Ctrl Logic: 0=internal, 1=external=PS_modeb_ext (bit 308 of SR)

Definition at line 214 of file FERS_Registers_520X.h.

◆ crcfg_ps_trg_source

#define crcfg_ps_trg_source 5

Peak Sens Trg source: 0=internal, 1=external (bit 309 of SR)

Definition at line 215 of file FERS_Registers_520X.h.

◆ crcfg_lg_pa_bias

#define crcfg_lg_pa_bias 6

LG Preamp bias: 0=normal, 1=weak (bit 323 of SR)

Definition at line 216 of file FERS_Registers_520X.h.

◆ crcfg_pa_fast_sh

#define crcfg_pa_fast_sh 7

Fast shaper connection: 0=high gain pa, 1=low gain pa (bit 328 of SR)

Definition at line 217 of file FERS_Registers_520X.h.

◆ crcfg_8bit_dac_ref

#define crcfg_8bit_dac_ref 8

HV adjust DAC reference: 0=2.5V, 1=4.5V (bit 330 of SR)

Definition at line 218 of file FERS_Registers_520X.h.

◆ crcfg_ota_bias

#define crcfg_ota_bias 9

Output OTA buffer bias auto off: 0=auto, 1=force on (bit 1133 of SR)

Definition at line 219 of file FERS_Registers_520X.h.

◆ crcfg_trg_polarity

#define crcfg_trg_polarity 10

Trigger polarity: 0=pos, 1=neg (bit 1141 of SR)

Definition at line 220 of file FERS_Registers_520X.h.

◆ crcfg_enable_chtrg

#define crcfg_enable_chtrg 11

Enable channel triggers (bit 1143 of SR)

Definition at line 221 of file FERS_Registers_520X.h.

◆ crcfg_enable_gtrg

#define crcfg_enable_gtrg 16

Enable propagation of gtrg to the Citiroc pin global_trig.

Definition at line 222 of file FERS_Registers_520X.h.

◆ crcfg_enable_veto

#define crcfg_enable_veto 17

Enable propagation of gate (= not veto) to the Citiroc pin val_evt.

Definition at line 223 of file FERS_Registers_520X.h.

◆ crcfg_repeat_raz

#define crcfg_repeat_raz 18

Enable loop asserting raz_chn until nor_charge stays active.

Definition at line 224 of file FERS_Registers_520X.h.

◆ SHAPING_TIME_12_5NS

#define SHAPING_TIME_12_5NS 6

Definition at line 226 of file FERS_Registers_520X.h.

◆ SHAPING_TIME_25NS

#define SHAPING_TIME_25NS 5

Definition at line 227 of file FERS_Registers_520X.h.

◆ SHAPING_TIME_37_5NS

#define SHAPING_TIME_37_5NS 4

Definition at line 228 of file FERS_Registers_520X.h.

◆ SHAPING_TIME_50NS

#define SHAPING_TIME_50NS 3

Definition at line 229 of file FERS_Registers_520X.h.

◆ SHAPING_TIME_62_5NS

#define SHAPING_TIME_62_5NS 2

Definition at line 230 of file FERS_Registers_520X.h.

◆ SHAPING_TIME_75NS

#define SHAPING_TIME_75NS 1

Definition at line 231 of file FERS_Registers_520X.h.

◆ SHAPING_TIME_87_5NS

#define SHAPING_TIME_87_5NS 0

Definition at line 232 of file FERS_Registers_520X.h.

◆ TEST_PULSE_SOURCE_EXT

#define TEST_PULSE_SOURCE_EXT 0

Definition at line 234 of file FERS_Registers_520X.h.

◆ TEST_PULSE_SOURCE_T0_IN

#define TEST_PULSE_SOURCE_T0_IN 1

Definition at line 235 of file FERS_Registers_520X.h.

◆ TEST_PULSE_SOURCE_T1_IN

#define TEST_PULSE_SOURCE_T1_IN 2

Definition at line 236 of file FERS_Registers_520X.h.

◆ TEST_PULSE_SOURCE_PTRG

#define TEST_PULSE_SOURCE_PTRG 3

Definition at line 237 of file FERS_Registers_520X.h.

◆ TEST_PULSE_SOURCE_SW_CMD

#define TEST_PULSE_SOURCE_SW_CMD 4

Definition at line 238 of file FERS_Registers_520X.h.

◆ TEST_PULSE_PREAMP_LG

#define TEST_PULSE_PREAMP_LG 1

Definition at line 240 of file FERS_Registers_520X.h.

◆ TEST_PULSE_PREAMP_HG

#define TEST_PULSE_PREAMP_HG 2

Definition at line 241 of file FERS_Registers_520X.h.

◆ TEST_PULSE_PREAMP_BOTH

#define TEST_PULSE_PREAMP_BOTH 3

Definition at line 242 of file FERS_Registers_520X.h.

◆ TEST_PULSE_DEST_ALL

#define TEST_PULSE_DEST_ALL 1

Definition at line 244 of file FERS_Registers_520X.h.

◆ TEST_PULSE_DEST_EVEN

#define TEST_PULSE_DEST_EVEN 2

Definition at line 245 of file FERS_Registers_520X.h.

◆ TEST_PULSE_DEST_ODD

#define TEST_PULSE_DEST_ODD 3

Definition at line 246 of file FERS_Registers_520X.h.

◆ TEST_PULSE_DEST_NONE

#define TEST_PULSE_DEST_NONE 4

Definition at line 247 of file FERS_Registers_520X.h.

◆ DPROBE_OFF

#define DPROBE_OFF 0

Definition at line 249 of file FERS_Registers_520X.h.

◆ DPROBE_PEAK_LG

#define DPROBE_PEAK_LG 1

Definition at line 250 of file FERS_Registers_520X.h.

◆ DPROBE_PEAK_HG

#define DPROBE_PEAK_HG 2

Definition at line 251 of file FERS_Registers_520X.h.

◆ DPROBE_HOLD

#define DPROBE_HOLD 3

Definition at line 252 of file FERS_Registers_520X.h.

◆ DPROBE_START_CONV

#define DPROBE_START_CONV 4

Definition at line 253 of file FERS_Registers_520X.h.

◆ DPROBE_DATA_COMMIT

#define DPROBE_DATA_COMMIT 5

Definition at line 254 of file FERS_Registers_520X.h.

◆ DPROBE_DATA_VALID

#define DPROBE_DATA_VALID 6

Definition at line 255 of file FERS_Registers_520X.h.

◆ DPROBE_CLK_1024

#define DPROBE_CLK_1024 7

Definition at line 256 of file FERS_Registers_520X.h.

◆ DPROBE_VAL_WINDOW

#define DPROBE_VAL_WINDOW 8

Definition at line 257 of file FERS_Registers_520X.h.

◆ DPROBE_T_OR

#define DPROBE_T_OR 9

Definition at line 258 of file FERS_Registers_520X.h.

◆ DPROBE_Q_OR

#define DPROBE_Q_OR 10

Definition at line 259 of file FERS_Registers_520X.h.

◆ DPROBE_XROC_TRG

#define DPROBE_XROC_TRG 11

Definition at line 260 of file FERS_Registers_520X.h.

◆ GAIN_SEL_AUTO

#define GAIN_SEL_AUTO 0

Definition at line 262 of file FERS_Registers_520X.h.

◆ GAIN_SEL_HIGH

#define GAIN_SEL_HIGH 1

Definition at line 263 of file FERS_Registers_520X.h.

◆ GAIN_SEL_LOW

#define GAIN_SEL_LOW 2

Definition at line 264 of file FERS_Registers_520X.h.

◆ GAIN_SEL_BOTH

#define GAIN_SEL_BOTH 3

Definition at line 265 of file FERS_Registers_520X.h.

◆ FAST_SHAPER_INPUT_HGPA

#define FAST_SHAPER_INPUT_HGPA 0

Definition at line 267 of file FERS_Registers_520X.h.

◆ FAST_SHAPER_INPUT_LGPA

#define FAST_SHAPER_INPUT_LGPA 1

Definition at line 268 of file FERS_Registers_520X.h.

◆ a_XR_ChControl

#define a_XR_ChControl ( i )

Value:

(0x0000 + (63-i))

Channel Settings (XROC channels are swapped on PCB => ch0 goes in ch63...)

Definition at line 280 of file FERS_Registers_520X.h.

◆ a_XR_ASIC_bias

#define a_XR_ASIC_bias 0x0040

ASIC biasing.

Definition at line 281 of file FERS_Registers_520X.h.

◆ a_XR_common_cfg

#define a_XR_common_cfg 0x0041

Common settings.

Definition at line 282 of file FERS_Registers_520X.h.

◆ a_XR_out_cfg

#define a_XR_out_cfg 0x0042

Output settings.

Definition at line 283 of file FERS_Registers_520X.h.

◆ a_XR_event_val

#define a_XR_event_val 0x0043

Event validation gating.

Definition at line 284 of file FERS_Registers_520X.h.

◆ a_pTDC_Control

#define a_pTDC_Control 0x0004

R/W - Magic word + reset bits.

Definition at line 362 of file FERS_Registers_520X.h.

◆ a_pTDC_Enable

#define a_pTDC_Enable 0x0008

R/W - Enable bits.

Definition at line 363 of file FERS_Registers_520X.h.

◆ a_pTDC_Header

#define a_pTDC_Header 0x000C

R/W - Event data format (header)

Definition at line 364 of file FERS_Registers_520X.h.

◆ a_pTDC_TrgWindow

#define a_pTDC_TrgWindow 0x0010

R/W - Trg Window Latency + Width.

Definition at line 365 of file FERS_Registers_520X.h.

◆ a_pTDC_Trg0Del_ToT

#define a_pTDC_Trg0Del_ToT 0x0014

R/W - Trg_Ch0 Delay + ToT.

Definition at line 366 of file FERS_Registers_520X.h.

◆ a_pTDC_BunchCount

#define a_pTDC_BunchCount 0x0018

R/W - Bunch Count Overflow + Offset.

Definition at line 367 of file FERS_Registers_520X.h.

◆ a_pTDC_EventID

#define a_pTDC_EventID 0x001C

R/W - EventID.

Definition at line 368 of file FERS_Registers_520X.h.

◆ a_pTDC_Ch_Control

#define a_pTDC_Ch_Control ( i )

Value:

(0x0020 + (i)*4)

R/W - Channel offset + some Ctrl bits.

Definition at line 369 of file FERS_Registers_520X.h.

◆ a_pTDC_Buffers

#define a_pTDC_Buffers 0x0120

R/W - Buffer settings.

Definition at line 370 of file FERS_Registers_520X.h.

◆ a_pTDC_Hit_RX_TX

#define a_pTDC_Hit_RX_TX 0x0124

R/W - Hit RX/TX.

Definition at line 371 of file FERS_Registers_520X.h.

◆ a_pTDC_DLL_TG

#define a_pTDC_DLL_TG 0x0128

R/W - DLL/TG.

Definition at line 372 of file FERS_Registers_520X.h.

◆ a_pTDC_PLL1

#define a_pTDC_PLL1 0x0130

R/W - PLL1.

Definition at line 373 of file FERS_Registers_520X.h.

◆ a_pTDC_PLL2

#define a_pTDC_PLL2 0x0134

R/W - PLL2.

Definition at line 374 of file FERS_Registers_520X.h.

◆ a_pTDC_Clocks

#define a_pTDC_Clocks 0x0138

Definition at line 375 of file FERS_Registers_520X.h.

◆ a_pTDC_ClockShift

#define a_pTDC_ClockShift 0x013C

Definition at line 376 of file FERS_Registers_520X.h.

◆ a_pTDC_Hit_RXen_T

#define a_pTDC_Hit_RXen_T 0x0140

Definition at line 377 of file FERS_Registers_520X.h.

◆ a_pTDC_Hit_RXen_B

#define a_pTDC_Hit_RXen_B 0x0144

Definition at line 378 of file FERS_Registers_520X.h.

◆ a_pTDC_PulseGen1

#define a_pTDC_PulseGen1 0x0148

Definition at line 379 of file FERS_Registers_520X.h.

◆ a_pTDC_PulseGen2

#define a_pTDC_PulseGen2 0x014C

Definition at line 380 of file FERS_Registers_520X.h.

◆ a_pTDC_PulseGen3

#define a_pTDC_PulseGen3 0x0150

Definition at line 381 of file FERS_Registers_520X.h.

◆ a_pTDC_ErrorFlagCtrl

#define a_pTDC_ErrorFlagCtrl 0x0154

Definition at line 382 of file FERS_Registers_520X.h.

◆ a_pTDC_Ch_Status

#define a_pTDC_Ch_Status ( i )

Value:

(0x0160 + (i)*4)

Definition at line 383 of file FERS_Registers_520X.h.

◆ a_pTDC_Trg_Status

#define a_pTDC_Trg_Status ( i )

Value:

(0x0260 + (i)*4)

Definition at line 384 of file FERS_Registers_520X.h.

◆ a_pTDC_RO_Status

#define a_pTDC_RO_Status ( i )

Value:

(0x0270 + (i)*4)

Definition at line 385 of file FERS_Registers_520X.h.

◆ a_pTDC_Cfg_Parity

#define a_pTDC_Cfg_Parity ( i )

Value:

(0x0280 + (i)*4)

Definition at line 386 of file FERS_Registers_520X.h.

◆ a_pTDC_PLL_Caps

#define a_pTDC_PLL_Caps 0x28C

Definition at line 387 of file FERS_Registers_520X.h.

◆ a_pTDC_DelayAdjust

#define a_pTDC_DelayAdjust 0xFFFC

Definition at line 388 of file FERS_Registers_520X.h.

◆ I2C_ADDR_TDC

#define I2C_ADDR_TDC ( i )

Value:

(0x63 - (i))

Definition at line 769 of file FERS_Registers_520X.h.

◆ I2C_ADDR_PLL0

#define I2C_ADDR_PLL0 0x68

Definition at line 770 of file FERS_Registers_520X.h.

◆ I2C_ADDR_PLL1

#define I2C_ADDR_PLL1 0x69

Definition at line 771 of file FERS_Registers_520X.h.

◆ I2C_ADDR_PLL2

#define I2C_ADDR_PLL2 0x70

Definition at line 772 of file FERS_Registers_520X.h.

◆ I2C_ADDR_EEPROM_MEM

#define I2C_ADDR_EEPROM_MEM 0x57

Definition at line 773 of file FERS_Registers_520X.h.

◆ I2C_ADDR_XR

#define I2C_ADDR_XR 0x78

Definition at line 774 of file FERS_Registers_520X.h.

Data Structures

Macros

Macro Definition Documentation

◆ _REGISTERS_H

◆ INDIV_ADDR

◆ BCAST_ADDR

◆ STATUS_READY

◆ STATUS_FAIL

◆ STATUS_RUNNING

◆ STATUS_TDL_SYNC

◆ STATUS_FPGA_OVERTEMP

◆ STATUS_TDC_RO_ERR

◆ STATUS_TDLINK_LOL

◆ STATUS_TDC0_LOL

◆ STATUS_TDC1_LOL

◆ STATUS_RO_CLK_LOL

◆ STATUS_TDL_DISABLED

◆ STATUS_TDC0_OVERTEMP

◆ STATUS_TDC1_OVERTEMP

◆ STATUS_BOARD_OVERTEMP

◆ STATUS_CRC_ERROR

◆ STATUS_UNUSED_15

◆ STATUS_SPI_BUSY

◆ STATUS_I2C_BUSY

◆ STATUS_I2C_FAIL

◆ crcfg_qdiscr_latch

◆ crcfg_sca_bias

◆ crcfg_pdet_mode_hg

◆ crcfg_pdet_mode_lg

◆ crcfg_ps_ctrl_logic

◆ crcfg_ps_trg_source

◆ crcfg_lg_pa_bias

◆ crcfg_pa_fast_sh

◆ crcfg_8bit_dac_ref

◆ crcfg_ota_bias

◆ crcfg_trg_polarity

◆ crcfg_enable_chtrg

◆ crcfg_enable_gtrg

◆ crcfg_enable_veto

◆ crcfg_repeat_raz

◆ SHAPING_TIME_12_5NS

◆ SHAPING_TIME_25NS

◆ SHAPING_TIME_37_5NS

◆ SHAPING_TIME_50NS

◆ SHAPING_TIME_62_5NS

◆ SHAPING_TIME_75NS

◆ SHAPING_TIME_87_5NS

◆ TEST_PULSE_SOURCE_EXT

◆ TEST_PULSE_SOURCE_T0_IN

◆ TEST_PULSE_SOURCE_T1_IN

◆ TEST_PULSE_SOURCE_PTRG

◆ TEST_PULSE_SOURCE_SW_CMD

◆ TEST_PULSE_PREAMP_LG

◆ TEST_PULSE_PREAMP_HG

◆ TEST_PULSE_PREAMP_BOTH

◆ TEST_PULSE_DEST_ALL

◆ TEST_PULSE_DEST_EVEN

◆ TEST_PULSE_DEST_ODD

◆ TEST_PULSE_DEST_NONE

◆ DPROBE_OFF

◆ DPROBE_PEAK_LG

◆ DPROBE_PEAK_HG

◆ DPROBE_HOLD

◆ DPROBE_START_CONV

◆ DPROBE_DATA_COMMIT

◆ DPROBE_DATA_VALID

◆ DPROBE_CLK_1024

◆ DPROBE_VAL_WINDOW

◆ DPROBE_T_OR

◆ DPROBE_Q_OR

◆ DPROBE_XROC_TRG

◆ GAIN_SEL_AUTO

◆ GAIN_SEL_HIGH

◆ GAIN_SEL_LOW

◆ GAIN_SEL_BOTH

◆ FAST_SHAPER_INPUT_HGPA

◆ FAST_SHAPER_INPUT_LGPA

◆ a_XR_ChControl

◆ a_XR_ASIC_bias

◆ a_XR_common_cfg