21#if (__STDC_VERSION__ >= 201112L) && !defined(__STDC_NO_THREADS__)
22#define THREAD_LOCAL _Thread_local
24#define THREAD_LOCAL __declspec(thread)
25#elif defined(__GNUC__)
26#define THREAD_LOCAL __thread
28#error unsupported compiler
31#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
34#include "FERS_MultiPlatform.h"
45extern int NumBoardConnected;
48extern uint16_t MaxEnergyRange;
262int Configure5202(
int handle,
int mode);
263int Configure5203(
int handle,
int mode);
264int Configure5204(
int handle,
int mode);
265int FERS_DumpBoardRegister5202(
int handle,
char* filename);
266int FERS_DumpBoardRegister5203(
int handle,
char* filename);
267int FERS_DumpBoardRegister5204(
int handle,
char* filename);
268int ConfigureProbe5202(
int handle);
269int ConfigureProbe5203(
int handle);
270int ConfigureProbe5204(
int handle);
272int Write_picoTDC_Cfg(
int handle,
int tdc,
picoTDC_Cfg_t pcfg,
int skipch);
273int Read_picoTDC_Cfg(
int handle,
int tdc,
picoTDC_Cfg_t* pcfg);
274int Save_picoTDC_Cfg(
int handle,
int tdc,
char* fname);
275int _setDefaultConfig(
int brd);
#define FERSLIB_MAX_NNODES
#define FERSLIB_MAX_NCH_5202
#define FERSLIB_MAX_NCH_5203
#define FERSLIB_MAX_NCH_5204
FERS board information structure.
FERS configuration parameters structure (lib + board)
int A5256_Ch0Polarity
Polarity of Ch0 in A5256 (POS, NEG)
uint16_t PAQ_Gain[64]
Gain of the Charge Preamp (Psiroc)
uint32_t GlitchFilterMode
DISABLED, TRAILING, LEADING, BOTH.
uint32_t HeaderField0
Header Field0 (for test only, default=4=near full flags (ch 0..7 of the port) - 00000CCCCCCCC)
uint32_t GWaddr[20]
Register Address.
uint32_t MuxNSmean
Num of samples for the Mux mean: 0: 4 samples, 1: 16 samples.
uint32_t TestMode
Run with fixed data patterns generated by the FPGA.
int StopRunMode
Stop Mode (for now, stop is always controlled by SW, but in the future it might be implemented in HW)
uint32_t Validation_Mode
Validation Mode: 0=disabled, 1=positive (accept), 2=negative (reject)
uint32_t T0_outMask
T0-OUT mask.
float TrefDelay
Tref delay in ns (can be negative)
uint32_t EnableServiceEvents
Enable service events.
uint16_t ZS_Threshold_HG[64]
Low Threshold for zero suppression (HG)
uint32_t TriggerLogic
Trigger Logic Definition.
uint32_t AnalogProbe[2]
Analog probe in XROC ASICs (Preamp LG/HG, Slow Shaper HG/LG, Fast Shaper)
int AcquisitionMode
Acquisition mode (Spectroscopy, Timing, Counting, etc...). Options are board dependent.
uint32_t CncProbe_B
Digital Probe in the concentrator (output FB)
int DisableThresholdCalib
Disable threshold calibration.
uint32_t WaveformLength
Num of samples in the waveform.
uint32_t PeakDetectorMode
Peaking Mode: 0 = Peak Stretcher, 1 = Track&Hold.
uint64_t TD2_Mask
Enable mask of Time Discriminator 2.
uint16_t PAQ_Comp[64]
Gain of the Charge Preamp (Psiroc)
uint16_t LG_Gain[64]
Gain of the Low Gain Preamp.
float ChTrg_Width
Self Trg Width in ns => Coinc windows for paired counting and trigger logic.
uint16_t ToT_reject_high_thr
The FPGA suppresses the Hits with ToT < high_threshold (0 disabled)
uint16_t HV_IndivAdj[64]
HV individual bias adjust (Citiroc 8bit input DAC)
uint32_t MaxPck_Block
Max. number of packets (events) that the concentrator can aggregate in one Data Block (0 = use defaul...
uint32_t MeasMode
LEAD_ONLY, LEAD_TRAIL, LEAD_TOT8, LEAD_TOT11.
float TempFeedbackCoeff
Temperature Feedback Coeff: Vout = Vset - k * (T-25)
uint32_t Enable_2nd_tstamp
Enable 2nd time stamp relative to the Tref signal.
uint16_t QD_FineThreshold[64]
Fine Threshold for Citiroc charge discriminator.
uint32_t MaxPck_Train
Max. number of packets (events) that the FERS unit can transmit to the concentrator in a single data ...
uint32_t LeadTrail_LSB
Leading/Trailing LSB required by the user: 0: LSB = ~3ps, N: LSB = 3ps * 2^N, (Max N=10; LSB = ~3....
uint32_t LG_ShapingTime
Shaping Time of the Low Gain preamp.
uint8_t OF_LimitedSize
Enable limited size on raw data output files.
uint32_t WaveformSource
LG0, HG0, LG1, HG1 (High/Low Gain, chip 0/1)
uint16_t TD1_FineThreshold[64]
Fine Threshold for Time discriminator 1.
uint32_t EnableToT
Enable readout of ToT (time over threshold) in A5202.
uint32_t Dis_tdl
Enable the TDL switching off when not used (DNIN: why is a parameter?)
float Tlogic_Width
TriggerLogic output width (0=linear)
uint64_t ChEnableMask
Channel enable mask (64 ch)
uint32_t FastShaperInput
Fast Shaper (Tdiscr) connection: 0 = High Gain PA, 1 = Low Gain PA.
uint32_t EnableCntZeroSuppr
Enable zero suppression in Counting Mode.
uint64_t Tlogic_Mask
Trigger Logic enable mask.
uint64_t ChEnableMask_e
Channel enable mask of Mezzanine expansion (128 ch, A5203 only)
uint32_t Veto_Mask
Veto mask.
int StartRunMode
Start Mode (this is a HW setting that defines how to start/stop the acquisition in the boards)
float TDCpulser_Period
picoTDC Pulser Output (period in ns)
uint16_t QD_CoarseThreshold
Coarse Threshold for Charge discriminator.
uint32_t TD_CoarseThreshold
Coarse Threshold for Citiroc time discriminator.
uint64_t QD_Mask
Enable mask of Charge Discriminator.
float HV_Vbias
Voltage setting for HV.
uint16_t TD2_FineThreshold[64]
Fine Threshold for Time discriminator 2.
float GateWidth
Gate window width in ns (will be rounded to steps of 25 ns)
uint32_t HeaderField1
Header Field1 (for test only, default=5=near full flags (ch 8..15 of the port + RO_buff,...
uint32_t Ch_Offset[128]
Channel Offset.
float TDCpulser_Width
picoTDC Pulser Output (width in ns)
uint32_t HG_ShapingTime
Shaping Time of the High Gain preamp.
uint32_t GWdata[20]
Data to write.
uint32_t Counting_Mode
Counting Mode (Singles, Paired_AND)
uint32_t Enable_HV_Adjust
Enable input DAC for HV fine adjust.
float DiscrThreshold[128]
Discriminator Threshold.
uint32_t TriggerMask
Bunch Trigger mask.
uint32_t Range_14bit
Use full 14 bit range for the A/D conversion.
uint32_t ProbeChannel[2]
Channel to probe.
float DiscrThreshold2[128]
Discriminator 2nd Threshold (double thershold mode only)
float TrgWindowOffset
Trigger window offset in ns; can be negative (will be rounded to steps of 25 ns)
uint16_t LG_ShapingTime_ind[64]
Shaping Time of the Low Gain preamp (individual)
uint32_t DigitalProbe[2]
Digital probe in XROC ASICs (peak Sens HG/LG) or FPGA (start_conv, data_commit...)
uint32_t GainSelect
Select gain between High/Low/Auto.
uint16_t TD2_CoarseThreshold
Coarse Threshold for Time discriminator 2.
int TestPulseSource
EXT, INT_T0, INT_T1, INT_PTRG, INT_SW.
uint32_t HighResClock
High Res clock distribution (MCX connectors)
float TrgHoldOff
Retrigger protection time. Set the busy active for N clock cycles (0=disabled)
uint64_t TOTD_Mask
Enable mask of TOT Discriminator (Psiroc)
uint32_t TestPulsePreamp
1=LG, 2=HG, 3=BOTH
uint16_t T_Gain[64]
T-Preamp gain.
uint64_t TD1_Mask
Enable mask of Time Discriminator 1.
uint16_t InputPolarity[64]
Preamp Input Polarity.
char OF_RawDataPath[200]
Raw data files saving path.
float PtrgPeriod
period in ns of the internal periodic trigger (dwell time)
uint32_t T1_outMask
T1-OUT mask.
uint32_t En_Empty_Ev_Suppr
Enable event suppression (only in Custom header mode)
uint16_t HG_ShapingTime_ind[64]
Shaping Time of the High Gain preamp (individual)
uint32_t EnableChannelTrgout
0 = Channel Trgout Disabled, 1 = Enabled (used in Citiroc only)
uint32_t TriggerBufferSize
Size of the trigger buffer in the FPGA (limits the number or pending triggers, already sent to the TD...
float FiberDelayAdjust[4][8][16]
Fiber length (in meters) for individual tuning of the propagation delay along the TDL daisy chains.
uint16_t TD_FineThreshold[64]
Fine Threshold for Citiroc time discriminator.
uint16_t HV_Adjust_Range
HV adj DAC range (reference): 0 = 2.5V, 1 = 4.5V, ?=DISABLED.
uint32_t CncProbe_A
Digital Probe in the concentrator (output FA)
float TrgWindowWidth
Trigger window width in ns (will be rounded to steps of 25 ns)
uint32_t EnableQdiscrLatch
Q-dicr mode: 1 = Latched, 0 = Direct.
uint32_t Tref_Mask
Tref mask.
float MuxClkPeriod
Period of the Mux Clock.
uint16_t Pedestal
Common pedestal added to all channels.
uint32_t En_Head_Trail
Enable Header and Trailer: 0=Keep all (group header+trail), 1=One word, 2=Header and trailer suppress...
uint32_t CncBufferSize
Data buffer size (in 32 bit words) in the concentrator; stop trains when this level is reached (0 = u...
uint16_t ToT_reject_low_thr
The FPGA suppresses the Hits with ToT > low_threshold (0 disabled)
uint16_t TOTD_FineThreshold[64]
Fine Threshold for TOT discriminator.
uint16_t TD1_CoarseThreshold
Coarse Threshold for Time discriminator 1.
uint16_t HG_Gain[64]
Gain of the High Gain Preamp.
uint32_t CitirocCfgMode
0=from regs, 1=from file
float TrefWindow
Tref Windows in ns (Common start/stop)
uint16_t ZS_Threshold_LG[64]
Low Threshold for zero suppression (LG)
uint32_t TDC_ChBufferSize
Channel buffer size in the picoTDC (set a limit to the max number of hits acquired by the channel)
uint32_t TdlClkPhase
Recovered clock phase shift: 0=0, 1=90, 2=180, 3=270.
uint32_t MajorityLevel
Majority Level.
uint32_t TestPulseAmplitude
DAC setting for the internal test pulser (12 bit). Meaningless for TestPulseSource=EXT.
uint32_t ToT_LSB
ToT LSB required by the user: 0: LSB = 3.125ps, N: LSB = 3.125ps * 2^N, (Max N=18; LSB = ~800 ns)
float HoldDelay
Time between Trigger and Hold.
int TestPulseDestination
-1=ALL, -2=EVEN, -3=ODD or channel number (0 to 63) for single channel pulsing
float TempSensCoeff[3]
Temperature Sensor Coefficients (2=quad, 1=lin, 0=offset)
uint64_t TD_Mask
Enable mask of Fast Shaper Discriminator (Psiroc)
uint32_t GWmask[20]
Bit Mask.
float MaxSizeDataOutputFile
Maximum size writable for raw data output files in bytes. Minimum size allowed 1 MB.
float HV_Imax
Imax for HV.
uint32_t TrgIdMode
Trigger ID: 0 = trigger counter, 1 = validation counter.
uint8_t OF_RawData
Enable saving raw data output files.
uint32_t Validation_Mask
Validation mask.
uint32_t GlitchFilterDelay
Delay of the glitch filter (~800 ps to ~10 ns with 16 steps)
int EnableTempFeedback
Enable Temp Feedback.
uint16_t TOTD_CoarseThreshold
Coarse Threshold for TOT discriminator.