x2745 DPP-PSD 2025052200
CUP documentation
Supported Parameters

Table of Contents

Digitizer General Parameters

CupVer

CUP version currently in use in the format "scope-YYYYMMDDNN", where YYYY is the year, MM the month, DD the day, and NN a progressive daily index of the release (e.g. scope-2021062900).

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

FPGA_FwVer

Build version of the FPGA firmware currently in use (e.g. "0.4.183").

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

FwType

Firmware type

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

ModelCode

CAEN code (e.g. WV2740XAAAAA)

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

PBCode

CAEN code of the PB (e.g. WA40BXAAAAAA)

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

ModelName

CAEN model name (e.g. V2740)

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

FormFactor

0=VME, 1=VME64X, 2=DT

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

FamilyCode

e.g. 2740, to indicate all versions of the XX2740 (VME, VME64X, desktop, SE/DIFF, etc...)

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

SerialNum

CAEN serial number (PID).

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

PCBrev_MB

PCB Revision of the Mother Board (e.g. 1).

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

PCBrev_PB

PCB Revision of the Piggyback (e.g. 1).

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

License

Product Unlock Code (PUC) for the DPP firmware only.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

LicenseStatus

License status

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Allowed Values:

  • Licensed: Licensed
  • NotLicensed: Not Licensed

LicenseRemainingTime

Remaining time in seconds to automatic run stop in case of not licensed or invalid license (DPP firmware only). A reboot is required to start a new acquisition. Always "0" in the case of Scope firmware; countdown from 30 minutes in the case of DPP firmware.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Max: 1800
  • Increment: 1
  • Unit of Measure: s

NumCh

Number of input-analog channles

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER

ADC_Nbit

ADC resolution in bits

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER

Energy_Nbit

Number of bits of the energy

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER

ADC_SamplRate

Sampling rate of the ADCs

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Unit of Measure: MS/s

InputRange

Input dynamic range.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Unit of Measure: V

InputType

Single ended or differential input type.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Zin

Input impedance of the analog channels

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Unit of Measure: OHM

ClockSource

This is the source of the system clock. Multiple options are not allowed

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Internal: Local oscillator, 62.5 MHz
  • FPClkIn: Front Panel Clock input

EnClockOutFP

Enables clock output on Front Panel for the daisy chain propagation of the clock between multiple boards.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • True: Enabled
  • False: Disabled

SFPLinkPresence

Check the presence of the SFP Link.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Allowed Values:

  • True: The SFP is correctly inserted.
  • False: The SFP is not present.

SFPLinkActive

Check the link status of SFP.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Allowed Values:

  • True: __
  • False: __

SFPLinkProtocol

Specify the link protocol of SFP

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Allowed Values:

  • Eth1G: 1 Gb Ethernet
  • Eth10G: 10 Gb Ethernet
  • CONET2: Conet2

IPAddress

IPv4 address of ethernet link

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Netmask

IPv4 netmask of ethernet link

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Gateway

IPv4 gateway of ethernet link

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Acquisition, Trigger, and Veto Parameters

StartSource

Defines the source for the start of run. Multiple options are allowed, separated by "|".

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • EncodedClkIn: Start from CLK-IN/SYNC connector on the front panel. This is a 4-pin connector (LVDS signals) used to propagate the reference clock (typ. 62.5 MHz) and a Sync signal. The rising edge of the Sync starts the acquisition, that lasts until the Sync returns low (falling edge).
  • SINlevel: Start from SIN (1=run, 0=stop)
  • SINedge: Start from SIN (rising edge = run; stop from SW)
  • SWcmd: Start from SW
  • LVDS: Start from LVDS
  • P0: Start from P0 (backplane)

GlobalTriggerSource

Defines the source for the Global Trigger, which is the signal that saves the events in the memory buffers. Multiple options are allowed, separated by "|".

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • TrgIn: Front Panel TRGIN
  • P0: Trigger from P0 (backplane)
  • SwTrg: Software trigger
  • LVDS: LVDS trgin
  • ITLA: Internal Trigger Logic A: combination of channel self-triggers
  • ITLB: Internal Trigger Logic B: combination of channel self-triggers
  • ITLA_AND_ITLB: Second level Trigger logic making the AND of ITL A and B
  • ITLA_OR_ITLB: Second level Trigger logic making the OR of ITL A and B
  • EncodedClkIn: Not implemented (encoded CLK-IN trigger)
  • GPIO: Front Panel GPIO
  • TestPulse: Internal Test Pulse
  • UserTrg: User custom trigger source

WaveTriggerSource

Allows to set the trigger source for the waveform. Setting this parameter means to get an event including the waveform and the associated time stamp and energy information.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: No trigger source enabled for the waveform
  • Ch64Trigger: One (or more) channel self-trigger can generate a trigger for a waveform
  • ChSelfTrigger: Channel self-trigger can generate a trigger for a waveform
  • SwTrg: Software Trigger can generate a trigger for a waveform
  • ADCOverSaturation: ADC Oversaturation can generate a trigger for a waveform
  • ADCUnderSaturation: ADC Undersaturation can generate a trigger for a waveform
  • ExternalInhibit: Inhibit can generate a trigger for a waveform
  • TRGIN: External TRGIN can generate a trigger for a waveform
  • GlobalTriggerSource: Acquisition Trigger Source (the same of the Scope mode) can generate a trigger for a waveform
  • LVDS: A signal on the LVDS connectors can generate a trigger for a waveform
  • ITLA: Internal Trigger Logic A can generate a trigger for a waveform
  • ITLB: Internal Trigger Logic B can generate a trigger for a waveform

EventTriggerSource

Allows to set the trigger source for a Time-Energy (T-E) event. Setting this parameter means to get an event including time stamp and energy information

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: No trigger source enabled for the T-E event
  • Ch64Trigger: One (or more) channel self-trigger can generate a trigger for a T-E event
  • ChSelfTrigger: Channel self-trigger can generate a trigger for a T-E event
  • SwTrg: Software Trigger can generate a trigger for a T-E event
  • TRGIN: External TRGIN can generate a trigger for a T-E event
  • GlobalTriggerSource: Acquisition Trigger Source (the same of the Scope mode) can generate a trigger for a T-E event
  • LVDS: A signal on the LVDS connectors can generate a trigger for a T-E event
  • ITLA: Internal Trigger Logic A can generate a trigger for a T-E event
  • ITLB: Internal Trigger Logic B can generate a trigger for a T-E event

ChannelsTriggerMask

Allows to set the mask over 64 bits to generate a channel trigger. It can be used to trigger a channel using a trigger coming from another channel. It also allows to set the mask over 64 bits to enable the channel to participate in the coincidence logic defined in CoincidenceMask and AntiCoincidenceMask(option Channel64Trg). 64-bit enable mask, each bit representing a channel.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

WaveSaving

Allows to save waveforms always or on request only.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Always: Waveforms are always saved
  • OnRequest: Waveforms are saved on request

TrgOutMode

Selects the signal that is routed to the TRGOUT output. Multiple options are not allowed.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Disabled: TRGOUT output disabled
  • TrgIn: Propagation of Front Panel TRGIN (TRGOUT is a replica, with some delay, of the TRGIN signal)
  • P0: Propagation of P0 trigger
  • SwTrg: Software trigger
  • LVDS: LVDS trgin
  • ITLA: Internal Trigger Logic A: combination of channel self-triggers
  • ITLB: Internal Trigger Logic B: combination of channel self-triggers
  • ITLA_AND_ITLB: Second level Trigger logic making the AND of ITL A and B
  • ITLA_OR_ITLB: Second level Trigger logic making the OR of ITL A and B
  • EncodedClkIn: Not implemented (propagation of the Encoded CLK-IN trigger)
  • Run: Propagation of the RUN signal (acquisition start/stop), before applying the delay given by the RunDelay parameter
  • RefClk: Monitor of the 62.5 MHz clock (used for phase alignment)
  • TestPulse: Internal Test Pulse
  • Busy: Busy of the board
  • UserTrgout: Trgout coming from the User Logic (open FPGA)
  • Fixed0: 0 level signal
  • Fixed1: 1 level signal
  • SyncIn: SyncIn signal
  • SIN: SIN connector signal
  • GPIO: GPIO connector signal
  • LBinClk: Internal Logic B clock signal
  • AcceptTrg: Accepted triggers signal
  • TrgClk: Tigger clock signal

GPIOMode

Selects the signal that is routed to the GPIO, when this is used as output. Multiple options are not allowed. The GPIO on the front panel is a bidirectional signal that can used in three different ways:

  1. As independent board output (each board drives its own GPIO)
  2. As a shared input for the boards: the signal is driven high (= 1) or low (= 0) by an external source and connected in "short circuit" among multiple boards using "T" connectors at the inputs. The GPIO is not internally terminated, thus it is necessary to put a 50 Ohm terminator at the end of the line (last "T"of the chain)
  3. As a shared bidirectional line, making a "wired OR". One or more boards can simultaneously drive the signal high (= 1). If no board drives the GPIO, it remains low (= 0). All boards can read back the signal. It is necessary to put a 50 Ohm terminator at both ends of the line (first and last "T" of the chain). This mode can be used to generate, for instance, the global Busy and Veto logic for multiple boards.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Disabled: GPIO disabled
  • TrgIn: Propagation of Front Panel TRGIN (GPIO is a replica, with some delay, of the TRGIN signal)
  • P0: Propagation of P0 trigger
  • SIN: Propagation of SIN
  • LVDS: LVDS trgin
  • ITLA: Internal Trigger Logic A: combination of channel self-triggers
  • ITLB: Internal Trigger Logic B: combination of channel self-triggers
  • ITLA_AND_ITLB: Second level Trigger logic making the AND of ITL A and B
  • ITLA_OR_ITLB: Second level Trigger logic making the OR of ITL A and B
  • EncodedClkIn: Not implemented (propagation of the Encoded CLK-IN trigger)
  • SwTrg: Software trigger
  • Run: Propagation of RUN
  • RefClk: Monitor of the 62.5 MHz clock (used for phase alignment)
  • TestPulse: Internal Test Pulse
  • Busy: Busy of the board
  • UserGPO: GPO coming from the User Logic (open FPGA)
  • Fixed0: 0 level signal
  • Fixed1: 1 level signal

BusyInSource

In a multi-board system, it might be necessary to prevent one board to accept a new trigger while another board is full and thus unable to accept the same trigger. For this reason, each board can generate a Busy signal to notify that it is unable to get a new trigger. If the busy/veto mechanism has some latency, it is advisable to generate the busy slightly before the digitizer become full. For this purpose, it is possible to assert the busy output when the acquisition memory reaches a certain level of occupancy (internally managed). The OR of the busy signals is typically used to stop the global trigger. It is possible to get the individual busy signals from each board and make an external OR logic or connect the boards with cables to propagate the Busy along the chain. Each board makes an OR between its internal busy and the busy input signal coming from the previous board, thus having a global Busy at the end of the line. This parameter defines the source of the Busy Input (schematized in the figure below)

Fig 1: Logic scheme of the BusyInSource

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: The Busy is given by the Internal Busy only (Memory full or almost full)
  • SIN: Busy input from SIN on front panel
  • GPIO: Busy input coming from GPIO on front panel, used as a simple input. It is also possible to use GPIO as a wired OR (bidirectional). In this mode, the Busy line goes high as soon as one board drives it high. All the boards can read the Busy line and use it as a veto for the trigger
  • LVDS: LVDS trgin

SyncOutMode

In a multi-board system, it can be useful to propagate a synchronous signal together with the clock (to synchronize the start of the run, for example) on CLK OUT front panel connector. This parameter defines which signal must be sent out. Multiple options are not allowed.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: SyncoutMode is disabled
  • SyncIn: SyncIn signal (if provided with clkIn on CLK IN connector)
  • TestPulse: Internal Test Pulse
  • IntClk: Internal 62.5 MHz clock (for test purposes)
  • Run: Propagation of RUN signal
  • User: _User custom _SyncoutMode__

BoardVetoSource

Defines the source for the Veto, which is the signal that inhibits the acquisition trigger. Multiple options are allowed, separated by "|". The VETO signal can be either active high or low, depending on the BoardVetoPolarity parameter. When active low, it acts as a GATE for the trigger. It is possible to stretch the duration of the VETO by means of the parameter.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: VETO is always OFF
  • SIN: SIN on the front panel
  • GPIO: GPIO on the front panel (used as input)
  • LVDS: LVDS trgin (see LVDSMode)
  • P0: P0 (signal from the backplane)
  • EncodedClkIn: Encoded CLK-IN veto (not implemented)

BoardVetoWidth

Whatever is the source of the VETO signal, it is possible to stretch the duration of the veto up to a given time by means of a re-triggerable monostable. Expressed in ns. When 0, the monostable is disabled and the veto lasts as long as the selected source is active.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 34359738360
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

BoardVetoPolarity

Defines the polarity of the Veto.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • ActiveHigh: Veto is active high. The signals acts as an "Inhibit" for the trigger
  • ActiveLow: Veto is active low. The signals acts as a "Gate" the trigger

ChannelVetoSource

Allows to set the veto for each channel; it can be external (which means one of the veto options in the previous table), or it can be on a channel base.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: Any channel veto source is disabled
  • BoardVeto: Enables board veto
  • ADCOverSaturation: Enables veto due to ADC oversaturation
  • ADCUnderSaturation: Enables veto due to ADC undersaturation

ADCVetoWidth

It is the width of the ADC veto (undersaturation and oversaturation width) expressed in ns.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 524280
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

RunDelay

When the start of run is controlled by a RUN signal that is propagated in daisy chain between the boards (for instance through the ClkIn- ClkOut or SIN-GPIO sync chain), it is necessary to compensate for the propagation delay and let the boards start exactly at the same time. The RunDelay parameter allows the start of the acquisition to be delayed by a given number of clock cycles with respect to the rising edge of the RUN signal. Assuming that the propagation delay is 2 cycles, the RunDelay setting will be 0 for the last board in the chain, 2 for the previous one, and so on up 2*(NB-1) for the first one.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 524280
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

EnAutoDisarmAcq

When enabled, the Auto Disarm option disarms the acquisition at the stop of run. When the start of run is controlled by an external signal, this option prevents the digitizer to restart without the intervention of the software.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • True: The acquisition is automatically disarmed after the stop. It is therefore necessary to rearm the digitizer (with the relevant command sent by the software) before starting a new run.
  • False: The acquisition is not disarmed after the stop. Multiple transition of the start signal will produce multiple runs.

AcquisitionStatus

Gets a 32 bit word representing the LED status.

Bit Number Name
0 Armed
1 Run
2 Run_mw
3 Jesd_Clk_Valid
4 Reserved
5 PreTriggerReady
6 LicenseFail
7-31 Not Used

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

VolatileClockOutDelay

Sets the delay of the clock output with respect to the input reference clock. When the clock is distributed in daisy chain between multiple boards (typ. through CLKIN-CLKOUT connectors), this option allows compensating the propagation delay and the fine alignment of the clock phases. This setting is directly written into the PLL registers and is not permanent. Once the optimal setting has been found, use the PermanentClockOutDelay parameter to store the delay in the flash memory and automatically reload it at every power-up.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: -18888.88888888889
  • Max: 18888.88888888889
  • Increment: 74.07407407407408
  • Set in Run: True
  • Unit of Measure: ps

PermanentClockOutDelay

Sets the VolatileClockOutDelay parameter, stores the value into the filesystem and makes it permanent. When read, it returns the value of the delay stored in the filesystem, that may differ from the one currently applied, if volatile.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: -18888.88888888889
  • Max: 18888.88888888889
  • Increment: 74.07407407407408
  • Set in Run: True
  • Unit of Measure: ps

SINFunction

Select the desired functionality of the S-IN connector for the selected channel. Multiple options are not allowed.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • None: The S-IN signal is not used.
  • ResetTimestamp: The S-IN signal resets the timestamp when high.

GPIFunction

Select the desired functionality of the G-IN connector for the selected channel. Multiple options are not allowed.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • None: The GPI signal is not used.
  • ResetTimestamp: The GPI signal resets the timestamp when high.

Waveform Parameters

ChRecordLengthS

The waveform size. Integer representing the number of samples. The actual size of the waveform will be automatically rounded to the closest allowed value. It is possible to get the exact size by reading back the parameter. The record length in time depends on wave resolution.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 4
  • Max: 8100
  • Increment: 4
  • Set in Run: False
  • Unit of Measure: S

ChRecordLengthT

The waveform size. Integer representing the time in ns. The actual size of the waveform will be automatically rounded to the closest allowed value. It is possible to get the exact size by reading back the parameter. The record length in time depends on wave resolution.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 32
  • Max: 64800
  • Increment: 32
  • Set in Run: False
  • Unit of Measure: ns

WaveDownsamplingFactor

Downsampling factor for the waveform resolution.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • 1: x1
  • 2: x2
  • 4: x4
  • 8: x8

WaveAnalogProbe0

Allows to set the analog signal for the analog probe 0.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • ADCInput: ADC input probe
  • ADCInputBaseline: ADC input baseline probe
  • CFDFilter: Constant Fraction Discriminator filter probe
  • ADCInput16: Enables 16-bit resolution for the ADC input probe instead of the default 14-bit. Selecting this option doubles the record length and disables WaveAnalogProbe1, WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, and WaveDigitalProbe3.

WaveAnalogProbe1

Allows to set the analog signal for the analog probe 1.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • ADCInput: ADC input probe
  • ADCInputBaseline: ADC input baseline probe
  • CFDFilter: Constant Fraction Discriminator filter probe

WaveDigitalProbe0

Allows to select the logical signal for digital probe 0.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Trigger: Trigger probe
  • CFDFilterArmed: Constant Fraction Discriminator Filter Armed probe
  • ReTriggerGuard: ReTrigger Guard probe
  • ADCInputBaselineFreeze: ADC Input Baseline Freeze probe
  • ADCInputOverthreshold: ADCInputOverthreshold
  • ChargeReady: Charge Ready probe
  • LongGate: Long Gate probe
  • PileUpTrigger: Pile Up Trigger probe
  • ShortGate: Short Gate probe
  • ChargeOverRange: Integrated Charge Over Range probe
  • ADCSaturation: ADC Saturation probe
  • ADCInputNegativeOverthreshold: ADC Input Negative Overthreshold probe

WaveDigitalProbe1

Allows to select the logical signal for digital probe 1.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Trigger: Trigger probe
  • CFDFilterArmed: Constant Fraction Discriminator Filter Armed probe
  • ReTriggerGuard: ReTrigger Guard probe
  • ADCInputBaselineFreeze: ADC Input Baseline Freeze probe
  • ADCInputOverthreshold: ADCInputOverthreshold
  • ChargeReady: Charge Ready probe
  • LongGate: Long Gate probe
  • PileUpTrigger: Pile Up Trigger probe
  • ShortGate: Short Gate probe
  • ChargeOverRange: Integrated Charge Over Range probe
  • ADCSaturation: ADC Saturation probe
  • ADCInputNegativeOverthreshold: ADC Input Negative Overthreshold probe

WaveDigitalProbe2

Allows to select the logical signal for digital probe 2.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Trigger: Trigger probe
  • CFDFilterArmed: Constant Fraction Discriminator Filter Armed probe
  • ReTriggerGuard: ReTrigger Guard probe
  • ADCInputBaselineFreeze: ADC Input Baseline Freeze probe
  • ADCInputOverthreshold: ADCInputOverthreshold
  • ChargeReady: Charge Ready probe
  • LongGate: Long Gate probe
  • PileUpTrigger: Pile Up Trigger probe
  • ShortGate: Short Gate probe
  • ChargeOverRange: Integrated Charge Over Range probe
  • ADCSaturation: ADC Saturation probe
  • ADCInputNegativeOverthreshold: ADC Input Negative Overthreshold probe

WaveDigitalProbe3

Allows to select the logical signal for digital probe 3.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Trigger: Trigger probe
  • CFDFilterArmed: Constant Fraction Discriminator Filter Armed probe
  • ReTriggerGuard: ReTrigger Guard probe
  • ADCInputBaselineFreeze: ADC Input Baseline Freeze probe
  • ADCInputOverthreshold: ADCInputOverthreshold
  • ChargeReady: Charge Ready probe
  • LongGate: Long Gate probe
  • PileUpTrigger: Pile Up Trigger probe
  • ShortGate: Short Gate probe
  • ChargeOverRange: Integrated Charge Over Range probe
  • ADCSaturation: ADC Saturation probe
  • ADCInputNegativeOverthreshold: ADC Input Negative Overthreshold probe

MaxRawDataSize

Maximum size that can be returned from a single call to GetData from the Raw endpoint

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Max: 0
  • Increment: 1
  • Unit of Measure: B

ChPreTriggerS

Number of samples coming before the position of the trigger in the waveform (i.e. size of the pre-trigger window).

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 4
  • Max: 1000
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: S

ChPreTriggerT

Time coming before the position of the trigger in the waveform (i.e. size of the pre-trigger window).

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 32
  • Max: 8000
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

WaveDataSource

In normal mode, the acquired waveform represents a sequence of ADC samples, resulting from the A/D conversion of the analog input. For test purposes, it is possible to replace the ADC data with internal data generators.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • ADC_DATA: Data from the ADC (normal operating mode)
  • ADC_TEST_TOGGLE: Toggle between 0x5555 and 0xAAAA (test mode)
  • ADC_TEST_RAMP: 16-bit ramp pattern (test mode)
  • ADC_TEST_SIN: 8-point sine wave test pattern
  • ADC_TEST_PRBS: 16-bit PRBS generated by a 23-bit PRBS pattern generator (test mode)
  • Ramp: Data from a ramp generator. It is actually a 16-bit field, where the 6 most significant bits identify the channel and the 10 less significant bits are the samples of a ramp from 0x000 up to 0x3FF (i.e. 0 to 1023). It is so a 10-bit ramp with offset given by "channel*1024". For channel 0, it is a counter from 0 to 1023; for channel 1, it is a counter from 1024 to 2047, and so on
  • IPE: Not implemented
  • SquareWave: Internally generated programmable square wave

Service Parameters

TestPulsePeriod

The Test Pulse is a programmable square wave that can be used as an internal periodic trigger (mainly for test purposes) or to generate a logic test pulse (TTL or NIM) on the TRGOUT and GPIO outputs. This parameter sets the period of the Test Pulse.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 34359738360
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

TestPulseWidth

Width of the Test Pulse (time that the signal stays high = 1).

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 34359738360
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

TestPulseLowLevel

Low level of the Test Pulse expressed in ADC counts

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 65535
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

TestPulseHighLevel

High level of the Test Pulse expressed in ADC counts

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 65535
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

IPEAmplitude

The new digitizers are equipped with an Internal Pulse Emulator capable of generating exponential pulses. This parameter determines the amplitude of the pulse.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 16383
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

IPEBaseline

Sets the offset of the exponantial pulses generated by the Internal Pulse Emulator.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 16383
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

IPEDecayTime

Sets the decay time of the exponantial pulses generated by the Internal Pulse Emulator.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 8
  • Max: 2000
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

IPERate

Sets the rate of the exponantial pulses generated by the Internal Pulse Emulator.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 1
  • Max: 60000
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: Hz

IPETimeMode

Selectes the time distribution of the Internal Pulse Emulator.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • ConstantRate: Pulse shapes are constant over time. It is possible to set the frequency using the IPERate parameter
  • Poissonian: The pulse rate follows a Poisson distribution. The average frequency value can be configured using the IPERate parameter

IOlevel

Sets the electrical logic level of the LEMO I/Os (TRGIN, SIN, TRGOUT, GPIO).

Note that TRGIN and SIN are internally terminated to 50 Ohm, while GPIO and TRGOUT require the termination to 50 Ohms at the receiver

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • NIM: NIM logic (0 = 0V, 1 = -0.8V, that is -16mA)
  • TTL: Low Voltage TLL logic (0 = 0V, 1 = 3.3V)

TempSensAirIn

Sensor monitoring the temperature of the incoming air flow of the board. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensAirOut

Sensor monitoring the temperature of the outcoming air flow of the board. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensCore

Sensor monitoring the temperature of the FPGA core. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensFirstADC

Sensor monitoring the temperature of the first ADC core. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensLastADC

Sensor monitoring the temperature of the last ADC core. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensHottestADC

Sensor monitoring the temperature of the last ADC core. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC0

Sensor monitoring the temperature of the ADC sensor #0. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC1

Sensor monitoring the temperature of the ADC sensor #1. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC2

Sensor monitoring the temperature of the ADC sensor #2. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC3

Sensor monitoring the temperature of the ADC sensor #3. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC4

Sensor monitoring the temperature of the ADC sensor #4. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC5

Sensor monitoring the temperature of the ADC sensor #5. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC6

Sensor monitoring the temperature of the ADC sensor #6. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensADC7

Sensor monitoring the temperature of the ADC sensor #7. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

TempSensDCDC

Sensor monitoring the temperature of the DC-DC converter. The resolution is 0.1 °C.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: °C

VInSensDCDC

Sensors monitoring the input voltage of the DC-DC converter. The resolution is 0.001 V.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.001
  • Set in Run: False
  • Unit of Measure: V

VOutSensDCDC

Sensors monitoring the output voltage of the DC-DC converter. The resolution is 0.001 V.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.001
  • Set in Run: False
  • Unit of Measure: V

IOutSensDCDC

Sensor monitoring the DC-DC converter current. The resolution is 0.001 A.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.001
  • Set in Run: False
  • Unit of Measure: A

FreqSensCore

Frequency of the DCDC converter. The resolution is 0.1 kHz.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: kHz

DutyCycleSensDCDC

Duty Cycle of the DCDC converter. The resolution is 0.1 percent.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 0.1
  • Set in Run: False
  • Unit of Measure: %

SpeedSensFan1

Sensor monitoring the fan speed #1 (desktop modules only). The resolution is 1 rpm.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: rpm

SpeedSensFan2

Sensor monitoring the fan speed #2 (desktop modules only). The resolution is 1 rpm.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: rpm

ErrorFlagMask

All these errors can be combined into a Global Error Flag through a masked OR, programmed by this parameter.

Bit Description
0 power_fail
1 board_init_fault
2 si5341_unlock
3 si5395_unlock
4 LMK04832_unlock
5 jesd_unlock
6 ddr_pl_bank0_calib_fail
7 ddr_pl_bank1_calib_fail
8 ddr_ps_calib_fail
9 fpga_config_fail
10 bic_error
11 adc_overtemp
12 air_overtemp
13 fpga_overtemp
14 dcdc_overtemp
15 clkin_miss
16 adc_shutdown

Additional information about the error bits is included in the Digitizer User Manual.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING

ErrorFlagDataMask

All these errors can be combined into a Data Error Flag through a masked OR, programmed by this parameter.

Bit Description
0 power_fail
1 board_init_fault
2 si5341_unlock
3 si5395_unlock
4 LMK04832_unlock
5 jesd_unlock
6 ddr_pl_bank0_calib_fail
7 ddr_pl_bank1_calib_fail
8 ddr_ps_calib_fail
9 fpga_config_fail
10 bic_error
11 adc_overtemp
12 air_overtemp
13 fpga_overtemp
14 dcdc_overtemp
15 clkin_miss
16 adc_shutdown

Additional information about the error bits is included in the Digitizer User Manual.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING

ErrorFlags

32 bit word with error flags.

Bit Description
0 power_fail
1 board_init_fault
2 si5341_unlock
3 si5395_unlock
4 LMK04832_unlock
5 jesd_unlock
6 ddr_pl_bank0_calib_fail
7 ddr_pl_bank1_calib_fail
8 ddr_ps_calib_fail
9 fpga_config_fail
10 bic_error
11 adc_overtemp
12 air_overtemp
13 fpga_overtemp
14 dcdc_overtemp
15 clkin_miss
16 adc_shutdown

Additional information about the error bits is included in the Digitizer User Manual.

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

BoardReady

Check if there is any error set in ErrorFlags

Options:

  • Level: DIG
  • Access Mode: READ_ONLY
  • Type: STRING

Allowed Values:

  • True: ErrorFlags is zero
  • False: Otherwise

ChRealtimeMonitor

RealTime measured by the FPGA, incremented with step of 524288 ns. Reading this parameter updates the values of ChDeadtimeMonitor, ChTriggerCnt, ChSavedEventCnt and ChWaveCnt.

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Unit of Measure: ns

ChDeadtimeMonitor

DeadTime measured by the FPGA, incremented with step of 524288 ns. Updated when reading ChRealtimeMonitor

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Unit of Measure: ns

ChTriggerCnt

Counter of channel triggers (24 bit), measured by FPGA. Updated when reading ChRealtimeMonitor.

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER

ChSavedEventCnt

Counter of channel saved events, measured by FPGA (24 bit). When activated, the coincident/anticoincident criteria are not considered. Updated when reading ChRealtimeMonitor.

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER

ChWaveCnt

Counter of channel events with waveform, measured by FPGA (24 bit). Updated when reading ChRealtimeMonito.

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER

Individual Trigger Parameters

EnDataReduction

If enabled, events consisting of 2 words are compressed in a single word event.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • True: Option enabled
  • False: Option disabled

ITLAMainLogic

Each channel of the digitizer feature a digital bipolar triangular filter discriminator with programmable rise time and threshold able to self-trigger on the input pulses and generate a self-trigger signal. In DPP Mode, the channels acquire independently, so the channel self-trigger is used locally to acquire a waveform. The trigger threshold is then referred to the bipolar triangular filter, and the threshold crossing arms the event selection. The trigger fires at the zero crossing of the time filter signal. The user can see the derivative trace on the signal inspector. It is also possible to combine all the self-triggers of the board, according to a specific trigger logic. There are two independent logic blocks, ITLA and ITLB. Their output can be used separately to feed, for instance, AcqTrigger and TrgOut, or combined in a second level trigger logic to implement more complex trigger schemes. Therefore, the ITLs can either generate the local acquisition trigger, common to all the channels, for the acquisition of the waveform, or propagate the signal outside, through the TRGOUT, thus making it possible to combine triggers of multiple boards in an external trigger logic, that eventually feeds back the TRGIN of the digitizers. Each ITL is made of an input enable mask (64 bits, one per channel), an optional pairing logic that combines the self triggers of two consecutive channels (e.g. paired coincidence) and the main trigger logic that combines the 64 selftriggers with an OR, AND or Majority logic. The output can be linear (no stretching) or reshaped by a programmable gate generator, either re-triggerable or not and finally programmed for polarity (direct or inverted).

Fig 2: Individual Trigger logic scheme

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • OR: ITLOUT = masked OR of channel self-triggers
  • AND: ITLOUT = masked AND of channel self-triggers
  • Majority: ITLOUT = masked Majority of channel self-triggers

ITLBMainLogic

Each channel of the digitizer feature a digital bipolar triangular filter discriminator with programmable rise time and threshold able to self-trigger on the input pulses and generate a self-trigger signal. In DPP Mode, the channels acquire independently, so the channel self-trigger is used locally to acquire a waveform. The trigger threshold is then referred to the bipolar triangular filter, and the threshold crossing arms the event selection. The trigger fires at the zero crossing of the time filter signal. The user can see the derivative trace on the signal inspector. It is also possible to combine all the self-triggers of the board, according to a specific trigger logic. There are two independent logic blocks, ITLA and ITLB. Their output can be used separately to feed, for instance, AcqTrigger and TrgOut, or combined in a second level trigger logic to implement more complex trigger schemes. Therefore, the ITLs can either generate the local acquisition trigger, common to all the channels, for the acquisition of the waveform, or propagate the signal outside, through the TRGOUT, thus making it possible to combine triggers of multiple boards in an external trigger logic, that eventually feeds back the TRGIN of the digitizers. Each ITL is made of an input enable mask (64 bits, one per channel), an optional pairing logic that combines the self triggers of two consecutive channels (e.g. paired coincidence) and the main trigger logic that combines the 64 selftriggers with an OR, AND or Majority logic. The output can be linear (no stretching) or reshaped by a programmable gate generator, either re-triggerable or not and finally programmed for polarity (direct or inverted).

Fig 3: Individual Trigger logic scheme

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • OR: ITLOUT = masked OR of channel self-triggers
  • AND: ITLOUT = masked AND of channel self-triggers
  • Majority: ITLOUT = masked Majority of channel self-triggers

ITLAMajorityLev

Defines the majority level of the Main Logic of the ITL A block. The majority output is calculated at every clock cycle, and it becomes TRUE when Nch >= MajLev, where Nch is the number of self-triggers active in that clock cycle and MajLev is the programmed majority level.

Note that when the Pair Logic is used to combine the self triggers two by two (AND/OR), each pair produces two identical signals that will be counted twice in the majority level.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 63
  • Increment: 1
  • Set in Run: False

ITLBMajorityLev

Defines the majority level of the Main Logic of the ITL B block. The majority output is calculated at every clock cycle, and it becomes TRUE when Nch >= MajLev, where Nch is the number of self-triggers active in that clock cycle and MajLev is the programmed majority level.

Note that when the Pair Logic is used to combine the self triggers two by two (AND/OR), each pair produces two identical signals that will be counted twice in the majority level.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 63
  • Increment: 1
  • Set in Run: False

ITLAPairLogic

Pairs of channels can be combined with an OR or AND before feeding in the Main trigger Logic. This is typically used in the readout of tubes or scintillator bars, where the two ends are read in coincidence, for instance in position sensitive detectors (the coincidence window will be set by the SelfTriggerWidth parameter). When the AND/OR logic is applied, the two outputs of the Pair Logic blocks are identical.

Note that they are counted twice in the following Majority logic. If the Pair Logic is disabled ("NONE" option), the block is transparent, and the two outputs are just a replica of the inputs.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • OR: Both Pair Logic Outputs = OR of two consecutive self-triggers
  • AND: Both Pair Logic Outputs = AND of two consecutive self-triggers
  • NONE: Outputs = Inputs

ITLBPairLogic

Pairs of channels can be combined with an OR or AND before feeding in the Main trigger Logic. This is typically used in the readout of tubes or scintillator bars, where the two ends are read in coincidence, for instance in position sensitive detectors (the coincidence window will be set by the SelfTriggerWidth parameter). When the AND/OR logic is applied, the two outputs of the Pair Logic blocks are identical.

Note that they are counted twice in the following Majority logic. If the Pair Logic is disabled ("NONE" option), the block is transparent, and the two outputs are just a replica of the inputs.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • OR: Both Pair Logic Outputs = OR of two consecutive self-triggers
  • AND: Both Pair Logic Outputs = AND of two consecutive self-triggers
  • NONE: Outputs = Inputs

ITLAPolarity

Polarity of the gate generator output.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Direct: Direct polarity
  • Inverted: Inverted polarity

ITLBPolarity

Polarity of the gate generator output.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Direct: Direct polarity
  • Inverted: Inverted polarity

ITLAMask

Enable mask (64 bits) as the inputs of the ITL A blocks. Each bit selects the corrisponding channel whose self triggers partecipate in the block logic. E.g. 0x3 (channel 0 and channel 1 partecipate in the trigger logic).

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

ITLBMask

Enable mask (64 bits) as the inputs of the ITL B blocks. Each bit selects the corrisponding channel whose self triggers partecipate in the block logic. E.g. 0x3 (channel 0 and channel 1 partecipate in the trigger logic).

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

ITLConnect

Alternative to ITLAMask, ITLBMask. Determines if the channel partecipate in ITLA or ITLB

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Disabled: The channel is disabled
  • ITLA: The channel participates in ITLA logic block
  • ITLB: The channel participates in ITLB logic block

ITLAGateWidth

Width of the gate generator at the output of the ITLA block. If set to 0, the gate operates in linear mode.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 524280
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

ITLBGateWidth

Width of the gate generator at the output of the ITLB block. If set to 0, the gate operates in linear mode.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 524280
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

LVDS Parameters

LVDSMode

The digitizer is equipped with 16 LVDS I/Os that can be programmed to be inputs or outputs by groups of 4 (quartets), depending on the LVDSDirection parameter. Once the direction has been selected, it is possible to select the functionality of the LVDS lines, individually for each quartet.

Options:

  • Level: LVDS
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • SelfTriggers: This option is available only when the LVDS are set as outputs. Each LVDS line can be assigned to a combination of the 64 self-triggers, implemented as a masked OR, where the mask is set by the LVDSTrgMask parameter(16 independent masks, one per LVDS line)
  • Sync: _Whatever is the direction of the quartet, the 4 lines are rigidly assigned to specific acquisition signals:

0 = Run 1 = Trigger 2 = Busy 3= Veto It is possible to implement a daisy chain distribution of these signals using one quartet as input and another one as output_

* IORegister: The LVDS lines of the quartet are statically controlled by the LVDSIOReg parameter. Use the SetValue function to set the relevant LVDS lines when programmed as output. Use GetValue to read the status of the LVDS lines when programmed as inputs.

  • User: User custom.

LVDSDirection

Assigns the direction to a quartet of LVDS I/Os.

Options:

  • Level: LVDS
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Input: The LVDS lines of the relevant quartet are used as input. The relevant LED on the front panel is OFF.
  • Output: The LVDS lines of the relevant quartet are used as output. The relevant LED on the front panel lights-up.

LVDSIOReg

Set the status of the LVDS I/O for the quartets when they are programmed to be output and Mode = IORegister. This parameter reads out the status of the quartets in the case the LVDS I/O are programmed as inputs (possibly externally driven).

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

LVDSTrgMask

Each LVDS line can be assigned to a combination of the 64 self-triggers, implemented as a masked OR, where the mask is set by this parameter. There are 16 independent masks, one per LVDS line. Note that the trigger mask assignment does not imply the LVDS direction and mode settings. It is therefore necessary to set the Direction = Output and Mode = SelfTriggers to use the Self-Trigger propagation to the LVDS I/Os.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Front Panel LEMO DAC Parameters

DACoutMode

Selects the signal type to be sent in output on the front panel DAC connector.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Static: DAC output stays at a fixed level, given by the DACoutStaticLevel parameter
  • Ramp: The DAC output is driven by a 14-bit counter
  • Sin5MHz: The DAC output is a sine wave at 5 MHz with fixed amplitude
  • Square: Square wave with period and with set by TestPulsePeriod and TestPulseWidth and amplitude between TestPulseLoweLevel and TestPulseHighLevel.
  • IPE: Not implemented
  • ChInput: The DAC reproduces the input signal received by one input channel, selected by the DACoutChSelect parameter
  • MemOccupancy: Level of the memory occupancy (not yet implemented)
  • ChSum: The DAC reproduces the "analog" sum of all the digitizer inputs (not yet implemented)
  • OverThrSum: The DAC output is proportional to the number of channels that are currently above the threshold

DACoutStaticLevel

When DACoutMode = Static, this parameter sets the 14-bit level of the DAC static output.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 16383
  • Increment: 1
  • Set in Run: True

DACoutChSelect

When DACoutMode = ChInput, the DAC reproduces the input signal of the channel selected by this parameter.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 63
  • Increment: 1
  • Set in Run: True

Input Signal Conditioning Parameters

SelfTriggerWidth

The output of the digital leading-edge comparator, that generates the self-trigger signal, can be used in "linear" mode (value set as 0), meaning that it lasts for the time the signal remains above (or below) the threshold, thus acting as an "Over-Threshold" signal, or can pass through a programmable gate generator that makes it a fixed-width pulse. The gate generator is a non-retriggerable monostable that goes high when the threshold is crossed and returns low after the programmed time. This parameter defines the fixed width of the overthreshold pulse.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 8184
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

InputDelay

Set input delay. The value is set at groups of 4 channels.

Options:

  • Level: GROUP
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 4095
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: S

EnOffsetCalibration

The input DC offset that determines the position of the signal baseline (zero Volts) is controlled by individual channel DACs. Due to the tolerance of the components, there is some spread in the offset setting that is compensated by the offset calibration. This is normally enabled and automatically applied in the firmware of the board. The calibration can be disabled, mainly when a new calibration must be calculated.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • True: DC offset calibration is applied (default)
  • False: DC offset calibration is not applied

ChEnable

Enable the channels for the acquisition, according to the Index. When the channel is disabled, it does not give any data and its self-trigger is off.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • True: The channel is enabled for the acquisition
  • False: The channel is disabled for the acquisition

SelfTrgRate

Each channel has a 32-bit counter permanently connected to its self-trigger This parameter allows to read the channel self-trigger rate in Hertz (Hz).

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: STRING
  • Unit of Measure: Hz

ChStatus

Gets a 32-bit word representing the status of the channel.

Bit Description
0 Error in setting the threshold which generates the over-threshold signal and the consequent trigger, if enabled.
1 Not used
23:2 Not used
31:24 Channel index (actually coded over 6 bits, so bit 31 and 30 are always 0)

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: STRING

DCOffset

A constant DC offset (controlled by a 16-bit DAC) is added to the analog input, individually for each channel, to adjust the position of the signal baseline (that is the "zero volt" of the analog input) within the dynamic range of the ADC. Because of the tolerance of the components, it is necessary to calibrate the offset DAC. The calibration is done by factory testing and normally it is not necessary to recalibrate the digitizer. It is however possible to perform a new calibration. The calibration parameters are stored in the flash memory of the board and loaded at power on. They are automatically applied by the internal logic every time the DCoffset parameter is written or read. DCoffset is expressed as a NUMBER number, in percent of the full-scale. When the DCoffset is 0, the baseline of the input signal is at 0 ADC counts. When the DCoffset is 100, the baseline of the input signal is at 2NBIT-1 ADC counts.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 100
  • Increment: 0.001
  • Set in Run: True
  • Unit of Measure: %

SignalOffset

Offset of the input signal.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: -1000000
  • Max: 1000000
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: uV

GainFactor

Reads the gain ADC calibration value stored in the internal flash. This value can be used by the user in its own DAQ software to calibrate the ADC and provide the signal amplitude value in milliVolts (mV) units.

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 1e-06
  • Set in Run: True

ADCToVolts

Returns the factor to convert ADC counts to volts.

Options:

  • Level: CH
  • Access Mode: READ_ONLY
  • Type: NUMBER
  • Min: 0
  • Increment: 1e-09
  • Set in Run: True
  • Unit of Measure: V

TriggerThr

Each channel of the digitizer has a digital leading-edge discriminator with programmable threshold able to self-trigger on the input pulses and generate a self-trigger signal (or an overthreshold signal) feeding the internal trigger logics or digitizer outputs. This parameter sets the trigger threshold. Typically, the value is relative to the baseline of the signal and the threshold is a 17-bit signed NUMBER number; in this case, the threshold automatically follows the baseline when the DCoffset parameter changes. Sometimes, it is preferable to set an absolute value for the threshold, referred to the ADC range. In this case, the threshold is unsigned NUMBER number.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 1
  • Max: 8191
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

PulsePolarity

Allows to set the polarity of the input pulse.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Positive: Positive polarity
  • Negative: Negative polarity

VGAGain

Sets the gain of the Variable Gain Amplifiers (VGA) in steps of 0.5 dB. The gain is set commonly to a group of 16 channels depending on the Index: Index[0] means CH0-CH15.

Options:

  • Level: VGA
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 40
  • Increment: 0.5
  • Set in Run: True
  • Unit of Measure: dB

Event Selection and Coincidence parameters

EnergySkimLowDiscriminator

Allows to flag events with energy higher than the low skim threshold. 16-bit value.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 65534
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: bin

EnergySkimHighDiscriminator

Allows to flag events with energy lower than the high skim threshold. 16-bit value.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 1
  • Max: 65535
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: bin

EventSelector

Allows to set which events have to be saved.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • All: All events are saved
  • PileUp: Only pileup events are saved
  • EnergySkim: Save only the events in the Energy Skim range

WaveSelector

Allows to set which waveform have to be saved.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • All: All waves are saved
  • PileUp: Only pileup waves are saved
  • EnergySkim: Save only waves in the Energy Skim range

EventNeutronReject

Enable Neutron Rejection for Events. See NeutronThreshold parameter

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: Neutron rejection for events is disabled.
  • Enabled: Neutron rejection for events is enabled.

WaveNeutronReject

Enable Neutron Rejection for Waves. See NeutronThreshold parameter

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: Neutron rejection for waves is disabled.
  • Enabled: Neutron rejection for waves is enabled.

CoincidenceMask

Allows to set the coincidence mask that generates a trigger on the specified channel.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: All the coincidence sources are disabled
  • Ch64Trigger: One of the 64 channels can generate a coincidence signal
  • TRGIN: TRGIN can generate a coincidence signal
  • GlobalTriggerSource: Acquisition Trigger can generate a coincidence signal
  • ITLA: ITLA can generate a coincidence signal
  • ITLB: ITLB can generate a coincidence signal

AntiCoincidenceMask

Allows to set the anticoincidence mask that generates a trigger on the specified channel.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Disabled: All the coincidence sources are disabled
  • Ch64Trigger: One of the 64 channels can generate a coincidence signal
  • TRGIN: TRGIN can generate a coincidence signal
  • GlobalTriggerSource: Acquisition Trigger can generate a coincidence signal
  • ITLA: ITLA can generate a coincidence signal
  • ITLB: ITLB can generate a coincidence signal

CoincidenceLengthS

Coincidence window length in samples (S). 16-bit value.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 65535
  • Increment: 1
  • Set in Run: True

CoincidenceLengthT

Coincidence window length in nanoseconds (ns). 16-bit value.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 524280
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

DPP Algorithm Parameters

SmoothingFactor

The smoothing is a moving average filter, where the input samples are replaced by the mean value of the previous n samples, where n is: 2, 4, 8 and 16 samples. When enabled (see TimeFilterSmoothing), the trigger is applied on the smoothed samples, thus reducing triggering on noise. Both CFD and LED triggering modes can be used on the smoothed input. The charge integration is either performed on the input samples and/or on the smoothed samples, according the ChargeSmoothing parameter.

Fig 4: Example of smoothing over four samples. The input samples are averaged over four samples and replaced in the smoothed samples by the mean value.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • 1: Smoothing is disabled.
  • 2: Smoothing is done averaging 2 samples.
  • 4: Smoothing is done averaging 4 samples.
  • 8: Smoothing is done averaging 8 samples.
  • 16: Smoothing is done averaging 16 samples.

ChargeSmoothing

Enable/Disable Smoothing factor for the charge evaluation.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Enabled: Smoothing factor is enabled in the charge evaluation
  • Disabled: Smoothing factor is disabled in the charge evaluation

TimeFilterSmoothing

Enable/Disable Smoothing factor for the time filter.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: True

Allowed Values:

  • Enabled: Smoothing factor is enabled for the time filter.
  • Disabled: Smoothing factor is disabled for the time filter.

TimeFilterRetriggerGuardT

In case of fast signal such as those coming from PMTs possible overshoots in the fast discriminator signal may occur causing a retrigger and so possible fake pile-up. This parameter allows to set a retrigger inhibit guard (in ns). 10-bit value.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 8000
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

TimeFilterRetriggerGuardS

In case of fast signal such as those coming from PMTs possible overshoots in the fast discriminator signal may occur causing a retrigger and so possible fake pile-up. This parameter allows to set a retrigger inhibit guard (in samples). 10-bit value.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 1000
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: S

TriggerHysteresis

When the input signal is no more over‐threshold, the trigger could fire again in the tail of the pulse, especially in case the tail contains spikes or noise. The “Trigger Hysteresis” feature inhibits any trigger until the input pulse reaches half of the threshold value itself. See for a diagram of this feature. This parameters allows to Enable/Disable Trigger hysteresis mechanism.

Fig 5: Trigger Hysteresis in DPP‐PSD firmware. Any other triggers are inhibited after the over‐threshold until the input reaches the value of half the threshold.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Disabled: Trigger hysteresis mechanism is disabled.
  • Enabled: Trigger hysteresis mechanism is enabled.

CFDDelayS

The x27xx digitizer running the DPP_PSD firmware discriminates events based on a CFD signal. The digital CFD signal has been implemented in the classical way except for the input signal inversion. The input waveform is first inverted, then attenuated by a factor f equal to the desired timing fraction (see CFDFraction) of full amplitude, then the signal is inverted again and delayed by a time d equal to the time it takes the pulse to rise from the constant fraction level to the pulse peak; the latest two signals are summed to produce a bipolar pulse, the CFD, and its zero crossing – corresponding to the fraction f of the input pulse – is taken as the trigger time.

The delay of the CFD signal can be defined by the user. The TriggerThreshold is then referred to the CFD itself, and the threshold crossing arms the event selection. The trigger fires at the zero crossing of the derivative signal itself.

Fig 6: Implementation of the Constant Fraction Discriminator. The input signal is first inverted to have a positive arming threshold, then attenuated by a factor f, then inverted again and delayed. The resulting signal has its zero-crossing corresponding to the set fraction f.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 1
  • Max: 1020
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: S

CFDDelayT

The x27xx digitizer running the DPP_PSD firmware discriminates events based on a CFD signal. The digital CFD signal has been implemented in the classical way except for the input signal inversion. The input waveform is first inverted, then attenuated by a factor f equal to the desired timing fraction (see CFDFraction) of full amplitude, then the signal is inverted again and delayed by a time d equal to the time it takes the pulse to rise from the constant fraction level to the pulse peak; the latest two signals are summed to produce a bipolar pulse, the CFD, and its zero crossing – corresponding to the fraction f of the input pulse – is taken as the trigger time.

The delay of the CFD signal can be defined by the user. The TriggerThreshold is then referred to the CFD itself, and the threshold crossing arms the event selection. The trigger fires at the zero crossing of the derivative signal itself.

Fig 7: Implementation of the Constant Fraction Discriminator. The input signal is first inverted to have a positive arming threshold, then attenuated by a factor f, then inverted again and delayed. The resulting signal has its zero-crossing corresponding to the set fraction f.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 8
  • Max: 8160
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

CFDFraction

CFD Fraction.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • 25: 25%
  • 50: 50%
  • 75: 75%
  • 100: 100%
  • Unit of Measure: %

TriggerFilterSelection

The DPP‐PSD allows the user to select the pulses according to two methods: leading edge, where a pulse is identified when its samples crosses a programmable threshold value, or through a digital constant fraction discrimination to have a better timing information. In both cases once the event is selected, the signal is delayed by a programmable number of samples (corresponding to the "pre‐trigger" value in ns) to be able to integrate the pulse before the trigger ("Pre‐Gate"). The gates for charge integration are then generated and received by the charge accumulator before the signal. While the gates are active, the baseline remains frozen until the last averaged value and its value is used as charge integration reference. For the whole duration of a programmable "retrigger guard" (see TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS) value, other trigger signals are inhibited. It is recommended to set a trigger hold‐off value compatible with the signal width. The baseline remains frozen for the whole trigger hold‐off duration. This parameter allows to set the Leading Edge or Constant Fraction Discriminator Filter selection

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • LeadingEdge: Set the Leading Edge discriminator
  • CFD: Set the Constant Fraction discriminator

ADCInputBaselineAvg

The digitizer continuously receives the input signal and digitizes it. The position of the signal baseline can be adjusted in the ADC scale to exploit the full dynamics of the digitizer using the DCOffset parameter. The baseline value is an important parameter of the DPP‐PSD firmware, since its value is used as a reference value for the charge integration of the input pulses. Moreover, most of the DPP parameters are related to the baseline value, like the trigger threshold. The user can set either a fixed value for the baseline or let the DPP firmware calculate it dynamically. In the first case the user must set the baseline value in LSB units through the option Fixed. This value remains fixed for the entire acquisition run. In the latter case, the firmware dynamically evaluates the baseline as the mean value of N points inside a moving time window. The user can choose one of the below listed option each of them corresponding to a predefined number of samples. The baseline is then frozen from few clocks before the gates start, up to the end of the maximum value between the long gate and the trigger hold‐off (see GateLongLengthT, GateLongLengthS and TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS). This parameter allows to set the Number of samples used to average the baseline of the Energy Filter.

Fig 8: Baseline calculation as managed by the DPP‐PSD algorithm

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • Fixed: Baseline fixed at AbsoluteBaseline value
  • Low: Baseline samples for average = 16
  • MediumLow: Baseline samples for average = 64
  • MediumHigh: Baseline samples for average = 256
  • High: Baseline samples for average = 1024

ADCInputBaselineGuardT

Energy Filter Baseline Evaluation Guard before the integration gate open in nanoseconds (ns).

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 8000
  • Increment: 8
  • Set in Run: True
  • Unit of Measure: ns

ADCInputBaselineGuardS

Energy Filter Baseline Evaluation Guard before the integration gate open in samples (S).

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 1000
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: S

PileupGap

The DPP‐PSD firmware is mainly designed to work with fast signals like those coming from scintillation detectors coupled with Photomultiplier Tubes. The relevant output signals do not show long decay tails as in the case of charge sensitive preamplifiers, and the probability of pile‐up between two pulses is quite low. In particular, the case of a second pulse sitting on the exponential tail of the previous one is rather rare. However, with the PSD algorithm, it is important to separate fast and slow components of the light emitted by the scintillation detector. Typically, the fast component is a quick pulse (few tens of ns) while the slow component is a quite long tail (typically a few μs) having amplitude much smaller than the fast component. To get the best results in the pulse shape discrimination, it is necessary to set the "Long Gate" as long as the full duration of the slow component. Under these conditions, most likely the events in pile‐up occur during the long gate and cause an error in the calculation of the charge of the slow component. For this reason, it is important to detect these cases. In the DPP‐PSD firmware, two events are considered in pile‐up when there is a situation of peak‐valley‐peak inside the same gate, where the gap between the valley and the peak is a programmable value. Referring to Figure 6, when the peak value is reached the algorithm evaluates the point corresponding to the PileupGap (PUR-GAP) value and gets ready to detect a pile‐up event (PILE‐UP ARMED). If there is a condition of "valley", and the input signal overcomes the PUR‐GAP threshold, then the event is tagged as pile‐up. In the default configuration the firmware does not take any action and the total charge of the event is evaluated within the gate and saved into memory.

This parameter allows to set the Peak Gap to identify pile up.

Fig 9: Pile‐up definition.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 65535
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

AbsoluteBaseline

Absolute value of the ADCInput signal baseline.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 65535
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

GateOffsetT

This parameter allows to set the Gate Offset with respect to the trigger signal.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 2000
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

GateOffsetS

This parameter allows to set the Gate Offset with respect to the trigger signal.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 250
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: S

GateLongLengthT

The aim of the DPP‐PSD firmware is to perform a charge integration of the input signal and to calculate the PSD factor performing a double gate integration of the input (Qshort and Qlong). Figure below shows the short and long gates position for two signals of different shapes. This parameter allows to set the Gate Long Length.

Fig 10: Long and short gate graphic position with respect to a couple of input pulses. The blue pulse has a longer tail than the red one.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 32000
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

GateLongLengthS

The aim of the DPP‐PSD firmware is to perform a charge integration of the input signal and to calculate the PSD factor performing a double gate integration of the input (Qshort and Qlong). Figure below shows the short and long gates position for two signals of different shapes. This parameter allows to set the Gate Long Length.

Fig 11: Long and short gate graphic position with respect to a couple of input pulses. The blue pulse has a longer tail than the red one.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 4000
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: S

GateShortLengthT

This parameter allows to set the Gate Short Length.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 32000
  • Increment: 8
  • Set in Run: False
  • Unit of Measure: ns

GateShortLengthS

This parameter allows to set the Gate Short Length.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 4000
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: S

LongChargeIntegratorPedestal

This parameter allows to set the Long Charge Integrator Pedestal. This feature is useful in case of energies close to zero.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 1000
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: ADC counts

ShortChargeIntegratorPedestal

This parameter allows to set the Long Charge Integrator Pedestal. This feature is useful in case of energies close to zero.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 1000
  • Increment: 1
  • Set in Run: False
  • Unit of Measure: ADC counts

EnergyGain

This parameter allows to set the Energy Gain i.e. to rescale the signal charge.

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • x1: Charge value is multiplied x1.
  • x4: Charge value is multiplied x4.
  • x16: Charge value is multiplied x16.
  • x64: Charge value is multiplied x64.
  • x256: Charge value is multiplied x256.

NeutronThreshold

This parameter allows to set the Neutron Energy Threshold for Neutron Discriminator. The FW compare the difference "Energy Long" – "Energy Short" (i.e. the difference between the charge integrated in the Long gate and in the Short gate) with the threshold set by this parameter to decide whether the event has to be rejected. Referring to the example of neutron/gamma discrimination shown in the figure below, the cut on PSD allows the user to reject most of the gamma events, thus recording only neutrons and the small amount of gamma overlapping with the neutrons.

Fig 12: 2D scatter plot of PSD parameter vs Energy in a neutron‐gamma application. On the left the 2D plot before the cut, on the right the plot after the cut on Neutron Threshold .

Options:

  • Level: CH
  • Access Mode: READ_WRITE
  • Type: NUMBER
  • Min: 0
  • Max: 1024
  • Increment: 1
  • Set in Run: True
  • Unit of Measure: ADC counts

EnStatEvents

If enabled, stats events are generated.

Options:

  • Level: DIG
  • Access Mode: READ_WRITE
  • Type: STRING
  • Set in Run: False

Allowed Values:

  • True: Stats event generation is enabled.
  • False: Stats event generation is disabled.