FERS configuration registers. More...

#define	a_acq_ctrl 0x01000000
	FERS configuration registers. More...

#define	a_run_mask 0x01000004
	Run mask: bit[0]=SW, bit[1]=T0-IN. More...

#define	a_trg_mask 0x01000008
	Global trigger mask: bit[0]=SW, bit[1]=T1-IN, bit[2]=Q-OR, bit[3]=Maj, bit[4]=Periodic. More...

#define	a_tref_mask 0x0100000C
	Tref mask: bit[0]=T0-IN, bit[1]=T1-IN, bit[2]=Q-OR, bit[3]=T-OR, bit[5]=Periodic. More...

#define	a_t0_out_mask 0x01000014
	T0 out mask. More...

#define	a_t1_out_mask 0x01000018
	T1 out mask. More...

#define	a_veto_mask 0x0100001C
	Veto mask: bit[0]=Cmd from TDL, bit[1]=T0-IN, bit[2]=T1-IN,. More...

#define	a_tref_delay 0x01000048
	Delay of the time reference for the coincidences. More...

#define	a_tref_window 0x0100004C
	Tref coincidence window (for list mode) More...

#define	a_dwell_time 0x01000050
	Dwell time (periodic trigger) in clk cyclces. 0 => OFF. More...

#define	a_list_size 0x01000054
	Number of 32 bit words in a packet in timing mode (list mode) More...

#define	a_pck_maxcnt 0x01000064
	Max num of packets transmitted to the TDL. More...

#define	a_channel_mask_0 0x01000100
	Input Channel Mask (ch 0 to 31) More...

#define	a_channel_mask_1 0x01000104
	Input Channel Mask (ch 32 to 63) More...

#define	a_fw_rev 0x01000300
	Firmware Revision. More...

#define	a_acq_status 0x01000304
	Acquisition Status. More...

#define	a_real_time 0x01000308
	Real Time in ms. More...

#define	a_dead_time 0x01000310
	Dead Time in ms. More...

#define	a_fpga_temp 0x01000348
	FPGA die Temperature. More...

#define	a_pid 0x01000400
	PID. More...

#define	a_pcb_rev 0x01000404
	PCB revision. More...

#define	a_fers_code 0x01000408
	Fers CODE (5202) More...

#define	a_rebootfpga 0x0100FFF0
	reboot FPGA from FW uploader More...

#define	a_test_led 0x01000228
	LED test mode. More...

#define	a_tdc_mode 0x0100022C
	TDC Mode. More...

#define	a_tdc_data 0x01000230
	TDC Data. More...

#define	a_sw_compatib 0x01004000
	SW compatibility. More...

#define	a_commands 0x01008000
	Send Commands (for Eth and USB) More...

#define	a_validation_mask 0x01000010
	Validation mask: bit[0]=Cmd from TDL, bit[1]=T0-IN, bit[2]=T1-IN. More...

#define	a_acq_ctrl2 0x01000020
	Acquisition Control Register 2. More...

#define	a_dprobe_5202 0x01000068
	Digital probes (signal inspector) More...

#define	a_citiroc_cfg 0x01000108
	Citiroc common configuration bits. More...

#define	a_citiroc_en 0x0100010C
	Citiroc internal parts enable mask. More...

#define	a_citiroc_probe 0x01000110
	Citiroc probes (signal inspector) More...

#define	a_qd_coarse_thr 0x01000114
	Coarse threshold for the Citiroc Qdiscr (10 bit DAC) More...

#define	a_td_coarse_thr 0x01000118
	Coarse threshold for the Citiroc Tdiscr (10 bit DAC) More...

#define	a_lg_sh_time 0x0100011C
	Low gain shaper time constant. More...

#define	a_hg_sh_time 0x01000120
	High gain shaper time constant. More...

#define	a_hold_delay 0x01000124
	Time from gtrg to peak hold. More...

#define	a_amux_seq_ctrl 0x01000128
	Timing parameters for the analog mux readout and conversion. More...

#define	a_wave_length 0x0100012C
	Waveform Length. More...

#define	a_scbs_ctrl 0x01000130
	Citiroc SC bit stream index and select. More...

#define	a_scbs_data 0x01000134
	Citiroc SC bit stream data. More...

#define	a_qdiscr_mask_0 0x01000138
	Charge Discriminator mask. More...

#define	a_qdiscr_mask_1 0x0100013C
	Charge Discriminator mask. More...

#define	a_tdiscr_mask_0 0x01000140
	Time Discriminator mask. More...

#define	a_tdiscr_mask_1 0x01000144
	Time Discriminator mask. More...

#define	a_tpulse_ctrl 0x01000200
	Test pulse mask. More...

#define	a_tpulse_dac 0x01000204
	Internal Test Pulse amplitude. More...

#define	a_hv_regaddr 0x01000210
	HV Register Address and Data Type. More...

#define	a_hv_regdata 0x01000214
	HV Register Data. More...

#define	a_trgho 0x01000218
	Trigger Hold off. More...

#define	a_dc_offset 0x01000220
	DAC for DC offset. More...

#define	a_spi_data 0x01000224
	SPI R/W data (for Flash Memory access) More...

#define	a_test_led 0x01000228
	LED test mode. More...

#define	a_tdc_mode 0x0100022C
	TDC Mode. More...

#define	a_tdc_data 0x01000230
	TDC Data. More...

#define	a_tlogic_def 0x01000234
	Trigger Logic Definition. More...

#define	a_tlogic_width 0x0100023C
	Monostable for Trigger logic output. More...

#define	a_hit_width 0x01000238
	Monostable for CR triggers. More...

#define	a_i2c_addr_5202 0x01000240
	I2C Addr. More...

#define	a_i2c_data_5202 0x01000244
	I2C Data. More...

#define	a_t_or_cnt 0x01000350
	T-OR counter. More...

#define	a_q_or_cnt 0x01000354
	Q-OR counter. More...

#define	a_hv_Vmon 0x01000356
	HV Vmon. More...

#define	a_hv_Imon 0x01000358
	HV Imon. More...

#define	a_hv_status 0x01000360
	HV Status. More...

#define	a_uC_status 0x01000600
	uC status More...

#define	a_uC_shutdown 0x01000604
	uC shutdown More...

#define	a_zs_lgthr 0x02000000
	Threshold for zero suppression (LG) More...

#define	a_zs_hgthr 0x02000004
	Threshold for zero suppression (HG) More...

#define	a_qd_fine_thr 0x02000008
	Fine individual threshold for the Citiroc Qdiscr (4 bit DAC) More...

#define	a_td_fine_thr 0x0200000C
	Fine individual threshold for the Citiroc Tdiscr (4 bit DAC) More...

#define	a_lg_gain 0x02000010
	Preamp Low Gain Setting. More...

#define	a_hg_gain 0x02000014
	Preamp High Gain Setting. More...

#define	a_hv_adj 0x02000018
	HV individual adjust (8 bit DAC) More...

#define	a_hitcnt 0x02000800
	Hit counters. More...

#define	a_io_ctrl 0x01000020
	I/O control. More...

#define	a_trg_delay 0x01000060
	Trigger delay. More...

#define	a_dprobe_5203 0x01000110
	Digital probe selection. More...

#define	a_lsof_almfull_bsy 0x01000068
	Almost Full level of LSOF (Event Data FIFO) to assert Busy. More...

#define	a_lsof_almfull_skp 0x0100006C
	Almost Full level of LSOF (Event Data FIFO) to skip data. More...

#define	a_trgf_almfull 0x01000070
	Almost Full level of Trigger FIFO. More...

#define	a_tot_rej_lthr 0x01000074
	ToT Reject Lower Threshold (0=disabled) More...

#define	a_tot_rej_hthr 0x01000078
	ToT Reject Higer Threshold (0=disabled) More...

#define	a_trg_hold_off 0x0100007A
	Retrigger protection time. Set the busy active for N clock cycles (0=disabled) More...

#define	a_strm_ptrg 0x0100007C
	Periodic trigger for streaming mode. More...

#define	a_i2c_addr_5203 0x01000200
	I2C Addr. More...

#define	a_i2c_data_5203 0x01000204
	I2C Data. More...

#define	a_trg_cnt 0x01000318
	Trigger counter. More...

#define	a_tdcro_status 0x0100031A
	TDC readout Status. More...

#define	a_rej_trg_cnt 0x0100031C
	Rejected Trigger counter. More...

#define	a_zs_trg_cnt 0x01000320
	Zero Suppressed Trigger counter. More...

#define	a_clk_out_phase 0x01000330
	Phase between TDC clock and FPGA clock (0x0000 = 0 deg; 0xFFFF = 180 deg) More...

#define	a_board_temp 0x01000350
	Board Temp. More...

#define	a_tdc0_temp 0x01000354
	TDC0 Temperature. More...

#define	a_tdc1_temp 0x01000358
	TDC1 Temperature. More...

#define	a_spi_data 0x01000224
	SPI R/W data (for Flash Memory access) More...

#define	a_tlogic_mask_0 0x01000140
	Trigger FPGA-Tlogic mask (in A5202 it corresponds to a_tdiscr_mask_0) More...

#define	a_tlogic_mask_1 0x01000144
	Trigger FPGA-Tlogic mask (in A5202 it corresponds to a_tdiscr_mask_1) More...

Detailed Description

FERS configuration registers.

Macro Definition Documentation

◆ a_acq_ctrl

#define a_acq_ctrl 0x01000000

FERS configuration registers.

Acquisition Control Register

Definition at line 40 of file FERS_Registers_520X.h.

◆ a_run_mask

#define a_run_mask 0x01000004

Run mask: bit[0]=SW, bit[1]=T0-IN.

Definition at line 41 of file FERS_Registers_520X.h.

◆ a_trg_mask

#define a_trg_mask 0x01000008

Global trigger mask: bit[0]=SW, bit[1]=T1-IN, bit[2]=Q-OR, bit[3]=Maj, bit[4]=Periodic.

Definition at line 42 of file FERS_Registers_520X.h.

◆ a_tref_mask

#define a_tref_mask 0x0100000C

Tref mask: bit[0]=T0-IN, bit[1]=T1-IN, bit[2]=Q-OR, bit[3]=T-OR, bit[5]=Periodic.

Definition at line 43 of file FERS_Registers_520X.h.

◆ a_t0_out_mask

#define a_t0_out_mask 0x01000014

T0 out mask.

Definition at line 44 of file FERS_Registers_520X.h.

◆ a_t1_out_mask

#define a_t1_out_mask 0x01000018

T1 out mask.

Definition at line 45 of file FERS_Registers_520X.h.

◆ a_veto_mask

#define a_veto_mask 0x0100001C

Veto mask: bit[0]=Cmd from TDL, bit[1]=T0-IN, bit[2]=T1-IN,.

Definition at line 46 of file FERS_Registers_520X.h.

◆ a_tref_delay

#define a_tref_delay 0x01000048

Delay of the time reference for the coincidences.

Definition at line 47 of file FERS_Registers_520X.h.

◆ a_tref_window

#define a_tref_window 0x0100004C

Tref coincidence window (for list mode)

Definition at line 48 of file FERS_Registers_520X.h.

◆ a_dwell_time

#define a_dwell_time 0x01000050

Dwell time (periodic trigger) in clk cyclces. 0 => OFF.

Definition at line 49 of file FERS_Registers_520X.h.

◆ a_list_size

#define a_list_size 0x01000054

Number of 32 bit words in a packet in timing mode (list mode)

Definition at line 50 of file FERS_Registers_520X.h.

◆ a_pck_maxcnt

#define a_pck_maxcnt 0x01000064

Max num of packets transmitted to the TDL.

Definition at line 51 of file FERS_Registers_520X.h.

◆ a_channel_mask_0

#define a_channel_mask_0 0x01000100

Input Channel Mask (ch 0 to 31)

Definition at line 52 of file FERS_Registers_520X.h.

◆ a_channel_mask_1

#define a_channel_mask_1 0x01000104

Input Channel Mask (ch 32 to 63)

Definition at line 53 of file FERS_Registers_520X.h.

◆ a_fw_rev

#define a_fw_rev 0x01000300

Firmware Revision.

Definition at line 54 of file FERS_Registers_520X.h.

◆ a_acq_status

#define a_acq_status 0x01000304

Acquisition Status.

Definition at line 55 of file FERS_Registers_520X.h.

◆ a_real_time

#define a_real_time 0x01000308

Real Time in ms.

Definition at line 56 of file FERS_Registers_520X.h.

◆ a_dead_time

#define a_dead_time 0x01000310

Dead Time in ms.

Definition at line 57 of file FERS_Registers_520X.h.

◆ a_fpga_temp

#define a_fpga_temp 0x01000348

FPGA die Temperature.

Definition at line 58 of file FERS_Registers_520X.h.

◆ a_pid

#define a_pid 0x01000400

PID.

Definition at line 59 of file FERS_Registers_520X.h.

◆ a_pcb_rev

#define a_pcb_rev 0x01000404

PCB revision.

Definition at line 60 of file FERS_Registers_520X.h.

◆ a_fers_code

#define a_fers_code 0x01000408

Fers CODE (5202)

Definition at line 61 of file FERS_Registers_520X.h.

◆ a_rebootfpga

#define a_rebootfpga 0x0100FFF0

reboot FPGA from FW uploader

Definition at line 62 of file FERS_Registers_520X.h.

◆ a_test_led [1/2]

#define a_test_led 0x01000228

LED test mode.

Test Mode for LEDs.

Definition at line 99 of file FERS_Registers_520X.h.

◆ a_tdc_mode [1/2]

#define a_tdc_mode 0x0100022C

TDC Mode.

R/W C 32 TDC modes.

Definition at line 100 of file FERS_Registers_520X.h.

◆ a_tdc_data [1/2]

#define a_tdc_data 0x01000230

TDC Data.

R/W C 32 Regs of TDC.

Definition at line 101 of file FERS_Registers_520X.h.

◆ a_sw_compatib

#define a_sw_compatib 0x01004000

SW compatibility.

Definition at line 67 of file FERS_Registers_520X.h.

◆ a_commands

#define a_commands 0x01008000

Send Commands (for Eth and USB)

Definition at line 68 of file FERS_Registers_520X.h.

◆ a_validation_mask

#define a_validation_mask 0x01000010

Validation mask: bit[0]=Cmd from TDL, bit[1]=T0-IN, bit[2]=T1-IN.

Definition at line 73 of file FERS_Registers_520X.h.

◆ a_acq_ctrl2

#define a_acq_ctrl2 0x01000020

Acquisition Control Register 2.

Definition at line 74 of file FERS_Registers_520X.h.

◆ a_dprobe_5202

#define a_dprobe_5202 0x01000068

Digital probes (signal inspector)

Definition at line 75 of file FERS_Registers_520X.h.

◆ a_citiroc_cfg

#define a_citiroc_cfg 0x01000108

Citiroc common configuration bits.

Definition at line 76 of file FERS_Registers_520X.h.

◆ a_citiroc_en

#define a_citiroc_en 0x0100010C

Citiroc internal parts enable mask.

Definition at line 77 of file FERS_Registers_520X.h.

◆ a_citiroc_probe

#define a_citiroc_probe 0x01000110

Citiroc probes (signal inspector)

Definition at line 78 of file FERS_Registers_520X.h.

◆ a_qd_coarse_thr

#define a_qd_coarse_thr 0x01000114

Coarse threshold for the Citiroc Qdiscr (10 bit DAC)

Definition at line 79 of file FERS_Registers_520X.h.

◆ a_td_coarse_thr

#define a_td_coarse_thr 0x01000118

Coarse threshold for the Citiroc Tdiscr (10 bit DAC)

Definition at line 80 of file FERS_Registers_520X.h.

◆ a_lg_sh_time

#define a_lg_sh_time 0x0100011C

Low gain shaper time constant.

Definition at line 81 of file FERS_Registers_520X.h.

◆ a_hg_sh_time

#define a_hg_sh_time 0x01000120

High gain shaper time constant.

Definition at line 82 of file FERS_Registers_520X.h.

◆ a_hold_delay

#define a_hold_delay 0x01000124

Time from gtrg to peak hold.

Definition at line 83 of file FERS_Registers_520X.h.

◆ a_amux_seq_ctrl

#define a_amux_seq_ctrl 0x01000128

Timing parameters for the analog mux readout and conversion.

Definition at line 84 of file FERS_Registers_520X.h.

◆ a_wave_length

#define a_wave_length 0x0100012C

Waveform Length.

Definition at line 85 of file FERS_Registers_520X.h.

◆ a_scbs_ctrl

#define a_scbs_ctrl 0x01000130

Citiroc SC bit stream index and select.

Definition at line 86 of file FERS_Registers_520X.h.

◆ a_scbs_data

#define a_scbs_data 0x01000134

Citiroc SC bit stream data.

Definition at line 87 of file FERS_Registers_520X.h.

◆ a_qdiscr_mask_0

#define a_qdiscr_mask_0 0x01000138

Charge Discriminator mask.

Definition at line 88 of file FERS_Registers_520X.h.

◆ a_qdiscr_mask_1

#define a_qdiscr_mask_1 0x0100013C

Charge Discriminator mask.

Definition at line 89 of file FERS_Registers_520X.h.

◆ a_tdiscr_mask_0

#define a_tdiscr_mask_0 0x01000140

Time Discriminator mask.

Definition at line 90 of file FERS_Registers_520X.h.

◆ a_tdiscr_mask_1

#define a_tdiscr_mask_1 0x01000144

Time Discriminator mask.

Definition at line 91 of file FERS_Registers_520X.h.

◆ a_tpulse_ctrl

#define a_tpulse_ctrl 0x01000200

Test pulse mask.

Definition at line 92 of file FERS_Registers_520X.h.

◆ a_tpulse_dac

#define a_tpulse_dac 0x01000204

Internal Test Pulse amplitude.

Definition at line 93 of file FERS_Registers_520X.h.

◆ a_hv_regaddr

#define a_hv_regaddr 0x01000210

HV Register Address and Data Type.

Definition at line 94 of file FERS_Registers_520X.h.

◆ a_hv_regdata

#define a_hv_regdata 0x01000214

HV Register Data.

Definition at line 95 of file FERS_Registers_520X.h.

◆ a_trgho

#define a_trgho 0x01000218

Trigger Hold off.

Definition at line 96 of file FERS_Registers_520X.h.

◆ a_dc_offset

#define a_dc_offset 0x01000220

DAC for DC offset.

Definition at line 97 of file FERS_Registers_520X.h.

◆ a_spi_data [1/2]

#define a_spi_data 0x01000224

SPI R/W data (for Flash Memory access)

Definition at line 146 of file FERS_Registers_520X.h.

◆ a_test_led [2/2]

#define a_test_led 0x01000228

LED test mode.

Test Mode for LEDs.

Definition at line 99 of file FERS_Registers_520X.h.

◆ a_tdc_mode [2/2]

#define a_tdc_mode 0x0100022C

TDC Mode.

R/W C 32 TDC modes.

Definition at line 100 of file FERS_Registers_520X.h.

◆ a_tdc_data [2/2]

#define a_tdc_data 0x01000230

TDC Data.

R/W C 32 Regs of TDC.

Definition at line 101 of file FERS_Registers_520X.h.

◆ a_tlogic_def

#define a_tlogic_def 0x01000234

Trigger Logic Definition.

Definition at line 102 of file FERS_Registers_520X.h.

◆ a_tlogic_width

#define a_tlogic_width 0x0100023C

Monostable for Trigger logic output.

Definition at line 103 of file FERS_Registers_520X.h.

◆ a_hit_width

#define a_hit_width 0x01000238

Monostable for CR triggers.

Definition at line 104 of file FERS_Registers_520X.h.

◆ a_i2c_addr_5202

#define a_i2c_addr_5202 0x01000240

I2C Addr.

Definition at line 105 of file FERS_Registers_520X.h.

◆ a_i2c_data_5202

#define a_i2c_data_5202 0x01000244

I2C Data.

Definition at line 106 of file FERS_Registers_520X.h.

◆ a_t_or_cnt

#define a_t_or_cnt 0x01000350

T-OR counter.

Definition at line 107 of file FERS_Registers_520X.h.

◆ a_q_or_cnt

#define a_q_or_cnt 0x01000354

Q-OR counter.

Definition at line 108 of file FERS_Registers_520X.h.

◆ a_hv_Vmon

#define a_hv_Vmon 0x01000356

HV Vmon.

Definition at line 109 of file FERS_Registers_520X.h.

◆ a_hv_Imon

#define a_hv_Imon 0x01000358

HV Imon.

Definition at line 110 of file FERS_Registers_520X.h.

◆ a_hv_status

#define a_hv_status 0x01000360

HV Status.

Definition at line 111 of file FERS_Registers_520X.h.

◆ a_uC_status

#define a_uC_status 0x01000600

uC status

Definition at line 112 of file FERS_Registers_520X.h.

◆ a_uC_shutdown

#define a_uC_shutdown 0x01000604

uC shutdown

Definition at line 113 of file FERS_Registers_520X.h.

◆ a_zs_lgthr

#define a_zs_lgthr 0x02000000

Threshold for zero suppression (LG)

Definition at line 114 of file FERS_Registers_520X.h.

◆ a_zs_hgthr

#define a_zs_hgthr 0x02000004

Threshold for zero suppression (HG)

Definition at line 115 of file FERS_Registers_520X.h.

◆ a_qd_fine_thr

#define a_qd_fine_thr 0x02000008

Fine individual threshold for the Citiroc Qdiscr (4 bit DAC)

Definition at line 116 of file FERS_Registers_520X.h.

◆ a_td_fine_thr

#define a_td_fine_thr 0x0200000C

Fine individual threshold for the Citiroc Tdiscr (4 bit DAC)

Definition at line 117 of file FERS_Registers_520X.h.

◆ a_lg_gain

#define a_lg_gain 0x02000010

Preamp Low Gain Setting.

Definition at line 118 of file FERS_Registers_520X.h.

◆ a_hg_gain

#define a_hg_gain 0x02000014

Preamp High Gain Setting.

Definition at line 119 of file FERS_Registers_520X.h.

◆ a_hv_adj

#define a_hv_adj 0x02000018

HV individual adjust (8 bit DAC)

Definition at line 120 of file FERS_Registers_520X.h.

◆ a_hitcnt

#define a_hitcnt 0x02000800

Hit counters.

Definition at line 121 of file FERS_Registers_520X.h.

◆ a_io_ctrl

#define a_io_ctrl 0x01000020

I/O control.

Definition at line 126 of file FERS_Registers_520X.h.

◆ a_trg_delay

#define a_trg_delay 0x01000060

Trigger delay.

Definition at line 127 of file FERS_Registers_520X.h.

◆ a_dprobe_5203

#define a_dprobe_5203 0x01000110

Digital probe selection.

Definition at line 128 of file FERS_Registers_520X.h.

◆ a_lsof_almfull_bsy

#define a_lsof_almfull_bsy 0x01000068

Almost Full level of LSOF (Event Data FIFO) to assert Busy.

Definition at line 129 of file FERS_Registers_520X.h.

◆ a_lsof_almfull_skp

#define a_lsof_almfull_skp 0x0100006C

Almost Full level of LSOF (Event Data FIFO) to skip data.

Definition at line 130 of file FERS_Registers_520X.h.

◆ a_trgf_almfull

#define a_trgf_almfull 0x01000070

Almost Full level of Trigger FIFO.

Definition at line 131 of file FERS_Registers_520X.h.

◆ a_tot_rej_lthr

#define a_tot_rej_lthr 0x01000074

ToT Reject Lower Threshold (0=disabled)

Definition at line 132 of file FERS_Registers_520X.h.

◆ a_tot_rej_hthr

#define a_tot_rej_hthr 0x01000078

ToT Reject Higer Threshold (0=disabled)

Definition at line 133 of file FERS_Registers_520X.h.

◆ a_trg_hold_off

#define a_trg_hold_off 0x0100007A

Retrigger protection time. Set the busy active for N clock cycles (0=disabled)

Definition at line 134 of file FERS_Registers_520X.h.

◆ a_strm_ptrg

#define a_strm_ptrg 0x0100007C

Periodic trigger for streaming mode.

Definition at line 135 of file FERS_Registers_520X.h.

◆ a_i2c_addr_5203

#define a_i2c_addr_5203 0x01000200

I2C Addr.

Definition at line 136 of file FERS_Registers_520X.h.

◆ a_i2c_data_5203

#define a_i2c_data_5203 0x01000204

I2C Data.

Definition at line 137 of file FERS_Registers_520X.h.

◆ a_trg_cnt

#define a_trg_cnt 0x01000318

Trigger counter.

Definition at line 138 of file FERS_Registers_520X.h.

◆ a_tdcro_status

#define a_tdcro_status 0x0100031A

TDC readout Status.

Definition at line 139 of file FERS_Registers_520X.h.

◆ a_rej_trg_cnt

#define a_rej_trg_cnt 0x0100031C

Rejected Trigger counter.

Definition at line 140 of file FERS_Registers_520X.h.

◆ a_zs_trg_cnt

#define a_zs_trg_cnt 0x01000320

Zero Suppressed Trigger counter.

Definition at line 141 of file FERS_Registers_520X.h.

◆ a_clk_out_phase

#define a_clk_out_phase 0x01000330

Phase between TDC clock and FPGA clock (0x0000 = 0 deg; 0xFFFF = 180 deg)

Definition at line 142 of file FERS_Registers_520X.h.

◆ a_board_temp

#define a_board_temp 0x01000350

Board Temp.

Definition at line 143 of file FERS_Registers_520X.h.

◆ a_tdc0_temp

#define a_tdc0_temp 0x01000354

TDC0 Temperature.

Definition at line 144 of file FERS_Registers_520X.h.

◆ a_tdc1_temp

#define a_tdc1_temp 0x01000358

TDC1 Temperature.

Definition at line 145 of file FERS_Registers_520X.h.

◆ a_spi_data [2/2]

#define a_spi_data 0x01000224

SPI R/W data (for Flash Memory access)

Definition at line 146 of file FERS_Registers_520X.h.

◆ a_tlogic_mask_0

#define a_tlogic_mask_0 0x01000140

Trigger FPGA-Tlogic mask (in A5202 it corresponds to a_tdiscr_mask_0)

Definition at line 151 of file FERS_Registers_520X.h.

◆ a_tlogic_mask_1

#define a_tlogic_mask_1 0x01000144

Trigger FPGA-Tlogic mask (in A5202 it corresponds to a_tdiscr_mask_1)

Definition at line 152 of file FERS_Registers_520X.h.