CAEN FERS Library
v1.1.4
SDK for FERS systems
FERS_Registers_5215.h
Go to the documentation of this file.
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#ifndef _REGISTERS_5215_H
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#define _REGISTERS_5215_H
// Protect against multiple inclusion
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// *****************************************************************
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// Virtual Registers of the concentrator
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// *****************************************************************
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// Register virtual address map
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#define VR_IO_STANDARD 0
// IO standard (NIM or TTL). Applies to all I/Os
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#define VR_IO_FA_DIR 1
// Direction of FA
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#define VR_IO_FB_DIR 2
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#define VR_IO_RA_DIR 3
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#define VR_IO_RB_DIR 4
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#define VR_IO_FA_FN 5
// Function of FA when used as output
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#define VR_IO_FB_FN 6
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#define VR_IO_RA_FN 7
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#define VR_IO_RB_FN 8
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#define VR_IO_FOUT_FN 9
// Funtion of the eigth F_OUT
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#define VR_IO_VETO_FN 10
// Veto source
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#define VR_IO_FIN_MASK 11
// F_IN enable mask
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#define VR_IO_FOUT_MASK 12
// F_OUT enable mask
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#define VR_IO_REG_VALUE 13
// Register controlled I/O
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#define VR_IO_TP_PERIOD 14
// Internal Test Pulse period
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#define VR_IO_TP_WIDTH 15
// Internal Test Pulse width
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#define VR_IO_CLK_SOURCE 16
// Clock source
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#define VR_IO_SYNC_OUT_A_FN 17
// Function of SYNC_OUT (RJ45)
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#define VR_IO_SYNC_OUT_B_FN 18
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#define VR_IO_SYNC_OUT_C_FN 19
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#define VR_IO_MASTER_SALVE 20
// Board is master or slave
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#define VR_IO_SYNC_PULSE_WIDTH 21
// Sync pulse width
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#define VR_IO_SYNC_SEND 22
// Send a sync pulse
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#define VR_SYNC_DELAY 23
// node to node delay in the daisy chain (used to fine tune the sync skew)
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#define VR_FIN_MAJORITY 24
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#define VR_IO_PPS_SOURCE 25
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#define VR_IO_PLL_STATUS 26
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#define VR_IO_LED_TEST_1 27
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#define VR_IO_LED_TEST_2 28
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#define VR_DMA_FLAGS_INFO 29
// Almost Full level of the INFO buffer (event descriptor table)
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#define VR_DMA_FLAGS_DATA 30
// Almost Full level of the DATA buffer (event payload)
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#define VR_ENABLED_LINKS 31
// Enable mask of the optical links
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#define VR_IO_DEBUG 32
// Digital Probes (allows some internal signals to be routed to the FA/FB outputs)
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// Register values
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#define VR_IO_SYNCSOURCE_ZERO 0
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#define VR_IO_SYNCSOURCE_SW_PULSE 1
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#define VR_IO_SYNCSOURCE_SW_REG 2
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#define VR_IO_SYNCSOURCE_FA 3
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#define VR_IO_SYNCSOURCE_FB 4
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#define VR_IO_SYNCSOURCE_RA 5
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#define VR_IO_SYNCSOURCE_RB 6
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#define VR_IO_SYNCSOURCE_GPS_PPS 7
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#define VR_IO_SYNCSOURCE_CLK_REF 8
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#define VR_IO_BOARD_MODE_MASTER 0
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#define VR_IO_BOARD_MODE_SLAVE 1
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#define VR_IO_STANDARD_IO_NIM 0
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#define VR_IO_STANDARD_IO_TLL 1
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#define VR_IO_DIRECTION_OUT 0
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#define VR_IO_DIRECTION_IN_R50 1
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#define VR_IO_DIRECTION_IN_HIZ 2
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#define VR_IO_FUNCTION_REGISTER 0
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#define VR_IO_FUNCTION_LOGIC_OR 1
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#define VR_IO_FUNCTION_LOGIC_AND 2
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#define VR_IO_FUNCTION_MAJORITY 3
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#define VR_IO_FUNCTION_TEST_PULSE 4
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#define VR_IO_FUNCTION_SYNC 5
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#define VR_IO_FUNCTION_FA_IN 6
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#define VR_IO_FUNCTION_FB_IN 7
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#define VR_IO_FUNCTION_RA_IN 8
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#define VR_IO_FUNCTION_RB_IN 9
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#define VR_IO_FUNCTION_ZERO 15
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#define VR_IO_CLKSOURCE_INTERNAL 0
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#define VR_IO_CLKSOURCE_LEMO 1
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#define VR_IO_CLKSOURCE_SYNC 2
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#define VR_IO_CLKSOURCE_RA 3
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// Digital Probes (for debug)
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#define VR_DPROBE_MON_TX_SYNC_SHORT 0x01
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#define VR_DPROBE_MON_TX_SYNC_ALIGN 0x02
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#define VR_DPROBE_MON_TX_SYNC_LONG 0x03
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#define VR_DPROBE_MON_TX_TIMING_SEND 0x04
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#define VR_DPROBE_MON_TX_NORMAL_SEND 0x05
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#define VR_DPROBE_MON_TX_TLAST_SEND 0x06
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#define VR_DPROBE_MON_TX_DATA_SEND 0x07
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#define VR_DPROBE_MON_TX_SYNC_PENDING 0x08
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#define VR_DPROBE_MON_TX_FIFOFULL 0x09
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#define VR_DPROBE_MON_TX_TVALID 0x0A
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#define VR_DPROBE_MON_TX_TREADY 0x0B
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#define VR_DPROBE_SC_BUSY 0x10
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#define VR_DPROBE_SC_DATA_WR 0x11
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#define VR_DPROBE_SC_INT_RD 0x12
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#define VR_DPROBE_SC_INT_WR 0x13
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#define VR_DPROBE_SC_COMMIT 0x14
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#define VR_DPROBE_SC_ACK 0x15
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#define VR_DPROBE_SC_NACK 0x16
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#define VR_DPROBE_STR_SOP 0x17
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#define VR_DPROBE_STR_EOP 0x18
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#define VR_DPROBE_STR_EOB 0x19
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#define VR_DPROBE_STR_DATA_VALID 0x20
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#define VR_DPROBE_CMD_BUSY 0x21
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#define VR_DPROBE_CMD_COMMIT 0x22
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#define VR_DPROBE_ENUMERATEBOARD 0x23
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#define VR_DPROBE_ENUMERATION_COMPLETED 0x24
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#define VR_DPROBE_SEND_T0 0x25
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#define VR_DPROBE_G_REINIT_LINK 0x26
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#define VR_DPROBE_READOUT_READY 0x27
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#define VR_DPROBE_MON_AXSM_WRITEREG 0x30
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#define VR_DPROBE_MON_AXSM_READREG 0x31
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#define VR_DPROBE_MON_AXSM_SENDCMD 0x32
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#define VR_DPROBE_MON_AXSM_SENDTOKEN 0x33
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#define VR_DPROBE_MON_AXSM_PENDING_TOKEN 0x34
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#define VR_DPROBE_MON_AXSM_PENDING_REG 0x35
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// TDlink error codes and status bits
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#define CNC_STATUS_INVALID_CHAIN 1
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#define CNC_STATUS_INVALID_BOARD 2
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#define CNC_STATUS_INVALID_FIRMWARE 3
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#define CNC_STATUS_CHAIN_NOT_INITIALIZED 4
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#define CNC_STATUS_UNABLE_TO_MAP_MEMORY_TO_USER_SPACE 5
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#define CNC_STATUS_UNABLE_TO_OPEN_DEV_MEM 6
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#define CNC_STATUS_UNABLE_TO_ALLOCATE_USER_MEMORY 7
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#define CNC_STATUS_UANBLE_TO_ALLOCATE_KERNEL_MEMORY 8
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#define CNC_STATUS_MEMORY_NOT_MAPPED 9
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#define CNC_STATUS_ADDRESS_OUT_OF_MEMORY 10
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#define CNC_STATUS_NO_MORE_SPACE 11
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#define CNC_STATUS_EMPTY 12
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#define CNC_STATUS_FULL 13
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#define CNC_STATUS_INVALID_SETTINGS 14
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#define CNC_STATUS_NO_MORE_SPACE_IN_THE_LIST 15
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#define CNC_STATUS_LIST_ALMOST_FULL 16
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#define CNC_STATUS_DMA_FAILED 17
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#define CNC_STATUS_CHAIN_DOWN 18
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#define CNC_STATUS_INVALID_IO_MODE 19
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#define CNC_STATUS_FPGA_IO_ERROR 20
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#define CNC_STATUS_IIC_IO_ERROR 21
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#define CNC_STATUS_INVALID_REGISTER 22
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#define CNC_STATUS_LINK_ERROR 23
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#define CNC_STATUS_UNABLE_TO_SET_LINK_PROP_DELAY 24
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#define CNC_STATUS_CHAIN_DISABLED 25
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#define CNC_STATUS_TIMEOUT 26
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#define CNC_STATUS_SFP_LOS 28
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#define CNC_STATUS_SFP_FAULT 29
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#endif
include
FERS_Registers_5215.h
Generated on Fri May 23 2025 15:56:15 for CAEN FERS Library by
1.9.2
1.9.2