Digitizer General Parameters

CupVer

CUP version currently in use in the format "scope-YYYYMMDDNN", where YYYY is the year, MM the month, DD the day, and NN a progressive daily index of the release (e.g. scope-2021062900).

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

FPGA_FwVer

Build version of the FPGA firmware currently in use (e.g. "0.4.183").

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

FwType

Firmware type

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

ModelCode

CAEN code (e.g. WV2740XAAAAA)

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

PBCode

CAEN code of the PB (e.g. WA40BXAAAAAA)

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

ModelName

CAEN model name (e.g. V2740)

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

FormFactor

0=VME, 1=VME64X, 2=DT

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

FamilyCode

e.g. 2740, to indicate all versions of the XX2740 (VME, VME64X, desktop, SE/DIFF, etc...)

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

SerialNum

CAEN serial number (PID).

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

PCBrev_MB

PCB Revision of the Mother Board (e.g. 1).

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

PCBrev_PB

PCB Revision of the Piggyback (e.g. 1).

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

License

Product Unlock Code (PUC) for the DPP firmware only.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

LicenseStatus

License status

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Allowed Values:

• Licensed: Licensed
• NotLicensed: Not Licensed

LicenseRemainingTime

Remaining time in seconds to automatic run stop in case of not licensed or invalid license (DPP firmware only). A reboot is required to start a new acquisition. Always "0" in the case of Scope firmware; countdown from 30 minutes in the case of DPP firmware.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Max: 1800
• Increment: 1
• Unit of Measure: s

NumCh

Number of input-analog channles

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER

ADC_Nbit

ADC resolution in bits

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER

ADC_SamplRate

Sampling rate of the ADCs

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Unit of Measure: MS/s

InputRange

Input dynamic range.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Unit of Measure: V

InputType

Single ended or differential input type.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Zin

Input impedance of the analog channels

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Unit of Measure: OHM

ClockSource

This is the source of the system clock. Multiple options are not allowed

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Internal: Local oscillator, 62.5 MHz
• FPClkIn: Front Panel Clock input

EnClockOutFP

Enables clock output on Front Panel for the daisy chain propagation of the clock between multiple boards.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• True: Enabled
• False: Disabled

SFPLinkPresence

Check the presence of the SFP Link.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Allowed Values:

• True: The SFP is correctly inserted.
• False: The SFP is not present.

SFPLinkActive

Check the link status of SFP.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Allowed Values:

• True: __
• False: __

SFPLinkProtocol

Specify the link protocol of SFP

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Allowed Values:

• Eth1G: 1 Gb Ethernet
• Eth10G: 10 Gb Ethernet
• CONET2: Conet2

IPAddress

IPv4 address of ethernet link

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Netmask

IPv4 netmask of ethernet link

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Gateway

IPv4 gateway of ethernet link

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Acquisition, Trigger, and Veto Parameters

StartSource

Defines the source for the start of run. Multiple options are allowed, separated by "|".

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• EncodedClkIn: Start from CLK-IN/SYNC connector on the front panel. This is a 4-pin connector (LVDS signals) used to propagate the reference clock (typ. 62.5 MHz) and a Sync signal. The rising edge of the Sync starts the acquisition, that lasts until the Sync returns low (falling edge).
• SINlevel: Start from SIN (1=run, 0=stop)
• SINedge: Start from SIN (rising edge = run; stop from SW)
• SWcmd: Start from SW
• LVDS: Start from LVDS
• P0: Start from P0 (backplane)

AcqTriggerSource

Defines the source for the Acquisition Trigger, which is the signal that opens the acquisition window and saves the waveforms in the memory buffers. Multiple options are allowed, separated by "|".

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: True

Allowed Values:

• TrgIn: Front Panel TRGIN
• P0: Trigger from P0 (backplane)
• SwTrg: Software trigger
• LVDS: LVDS trgin
• ITLA: Internal Trigger Logic A: combination of channel self-triggers
• ITLB: Internal Trigger Logic B: combination of channel self-triggers
• ITLA_AND_ITLB: Second level Trigger logic making the AND of ITL A and B
• ITLA_OR_ITLB: Second level Trigger logic making the OR of ITL A and B
• EncodedClkIn: Not implemented (encoded CLK-IN trigger)
• GPIO: Front Panel GPIO
• TestPulse: Internal Test Pulse
• UserTrg: User custom trigger source

TrgOutMode

Selects the signal that is routed to the TRGOUT output. Multiple options are not allowed.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Disabled: TRGOUT output disabled
• TrgIn: Propagation of Front Panel TRGIN (TRGOUT is a replica, with some delay, of the TRGIN signal)
• P0: Propagation of P0 trigger
• SwTrg: Software trigger
• LVDS: LVDS trgin
• ITLA: Internal Trigger Logic A: combination of channel self-triggers
• ITLB: Internal Trigger Logic B: combination of channel self-triggers
• ITLA_AND_ITLB: Second level Trigger logic making the AND of ITL A and B
• ITLA_OR_ITLB: Second level Trigger logic making the OR of ITL A and B
• EncodedClkIn: Not implemented (propagation of the Encoded CLK-IN trigger)
• Run: Propagation of the RUN signal (acquisition start/stop), before applying the delay given by the RunDelay parameter
• RefClk: Monitor of the 62.5 MHz clock (used for phase alignment)
• TestPulse: Internal Test Pulse
• Busy: Busy of the board
• UserTrgout: Trgout coming from the User Logic (open FPGA)
• Fixed0: 0 level signal
• Fixed1: 1 level signal
• SyncIn: SyncIn signal
• SIN: SIN connector signal
• GPIO: GPIO connector signal
• LBinClk: Internal Logic B clock signal
• AcceptTrg: Accepted triggers signal
• TrgClk: Tigger clock signal

GPIOMode

Selects the signal that is routed to the GPIO, when this is used as output. Multiple options are not allowed. The GPIO on the front panel is a bidirectional signal that can used in three different ways:

1. As independent board output (each board drives its own GPIO)
2. As a shared input for the boards: the signal is driven high (= 1) or low (= 0) by an external source and connected in "short circuit" among multiple boards using "T" connectors at the inputs. The GPIO is not internally terminated, thus it is necessary to put a 50 Ohm terminator at the end of the line (last "T"of the chain)
3. As a shared bidirectional line, making a "wired OR". One or more boards can simultaneously drive the signal high (= 1). If no board drives the GPIO, it remains low (= 0). All boards can read back the signal. It is necessary to put a 50 Ohm terminator at both ends of the line (first and last "T" of the chain). This mode can be used to generate, for instance, the global Busy and Veto logic for multiple boards.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Disabled: GPIO disabled
• TrgIn: Propagation of Front Panel TRGIN (GPIO is a replica, with some delay, of the TRGIN signal)
• P0: Propagation of P0 trigger
• SIN: Propagation of SIN
• LVDS: LVDS trgin
• ITLA: Internal Trigger Logic A: combination of channel self-triggers
• ITLB: Internal Trigger Logic B: combination of channel self-triggers
• ITLA_AND_ITLB: Second level Trigger logic making the AND of ITL A and B
• ITLA_OR_ITLB: Second level Trigger logic making the OR of ITL A and B
• EncodedClkIn: Not implemented (propagation of the Encoded CLK-IN trigger)
• SwTrg: Software trigger
• Run: Propagation of RUN
• RefClk: Monitor of the 62.5 MHz clock (used for phase alignment)
• TestPulse: Internal Test Pulse
• Busy: Busy of the board
• UserGPO: GPO coming from the User Logic (open FPGA)
• Fixed0: 0 level signal
• Fixed1: 1 level signal

BusyInSource

In a multi-board system, it might be necessary to prevent one board to accept a new trigger while another board is full and thus unable to accept the same trigger. For this reason, each board can generate a Busy signal to notify that it is unable to get a new trigger. If the busy/veto mechanism has some latency, it is advisable to generate the busy slightly before the digitizer become full. For this purpose, it is possible to assert the busy output when the acquisition memory reaches a certain level of occupancy (internally managed). The OR of the busy signals is typically used to stop the global trigger. It is possible to get the individual busy signals from each board and make an external OR logic or connect the boards with cables to propagate the Busy along the chain. Each board makes an OR between its internal busy and the busy input signal coming from the previous board, thus having a global Busy at the end of the line. This parameter defines the source of the Busy Input (schematized in the figure below)

Fig 1: Logic scheme of the BusyInSource

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: True

Allowed Values:

• Disabled: The Busy is given by the Internal Busy only (Memory full or almost full)
• SIN: Busy input from SIN on front panel
• GPIO: Busy input coming from GPIO on front panel, used as a simple input. It is also possible to use GPIO as a wired OR (bidirectional). In this mode, the Busy line goes high as soon as one board drives it high. All the boards can read the Busy line and use it as a veto for the trigger
• LVDS: LVDS trgin

SyncOutMode

In a multi-board system, it can be useful to propagate a synchronous signal together with the clock (to synchronize the start of the run, for example) on CLK OUT front panel connector. This parameter defines which signal must be sent out. Multiple options are not allowed.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: True

Allowed Values:

• Disabled: SyncoutMode is disabled
• SyncIn: SyncIn signal (if provided with clkIn on CLK IN connector)
• TestPulse: Internal Test Pulse
• IntClk: Internal 62.5 MHz clock (for test purposes)
• Run: Propagation of RUN signal
• User: _User custom _SyncoutMode__

VetoSource

Defines the source for the Veto, which is the signal that inhibits the acquisition trigger. Multiple options are allowed, separated by "|". The VETO signal can be either active high or low, depending on the VetoPolarity parameter. When active low, it acts as a GATE for the trigger. It is possible to stretch the duration of the VETO by means of the parameter VetoWidth.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: True

Allowed Values:

• Disabled: VETO is always OFF
• SIN: SIN on the front panel
• GPIO: GPIO on the front panel (used as input)
• LVDS: LVDS trgin
• P0: P0 (signal from the backplane)
• EncodedClkIn: Not implemented (encoded CLK-IN veto)

VetoWidth

Whatever is the source of the VETO signal, it is possible to stretch the duration of the veto up to a given time by means of a re-triggerable monostable. When 0, the monostable is disabled and the veto lasts as long as the selected source is active.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 34359738360
• Increment: 8
• Set in Run: True
• Unit of Measure: ns

VetoPolarity

Defines the polarity of the Veto

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: True

Allowed Values:

• ActiveHigh: Veto is active high. The signal acts as an "Inhibit" for the trigger
• ActiveLow: Veto is active low. The signal acts as a "Gate" the trigger

RunDelay

When the start of run is controlled by a RUN signal that is propagated in daisy chain between the boards (for instance through the ClkIn- ClkOut or SIN-GPIO sync chain), it is necessary to compensate for the propagation delay and let the boards start exactly at the same time. The RunDelay parameter allows the start of the acquisition to be delayed by a given number of clock cycles with respect to the rising edge of the RUN signal. Assuming that the propagation delay is 2 cycles, the RunDelay setting will be 0 for the last board in the chain, 2 for the previous one, and so on up 2*(NB-1) for the first one.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 524280
• Increment: 8
• Set in Run: False
• Unit of Measure: ns

EnAutoDisarmAcq

When enabled, the Auto Disarm option disarms the acquisition at the stop of run. When the start of run is controlled by an external signal, this option prevents the digitizer to restart without the intervention of the software.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• True: The acquisition is automatically disarmed after the stop. It is therefore necessary to rearm the digitizer (with the relevant command sent by the software) before starting a new run.
• False: The acquisition is not disarmed after the stop. Multiple transition of the start signal will produce multiple runs.

AcquisitionStatus

Gets a 32 bit word representing the LED status.

Bit Number	Name
0	Armed
1	Run
2	Run_mw
3	Jesd_Clk_Valid
4	Busy
5	PreTriggerReady
6	LicenseFail
7-31	Not Used

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

VolatileClockOutDelay

Sets the delay of the clock output with respect to the input reference clock. When the clock is distributed in daisy chain between multiple boards (typ. through CLKIN-CLKOUT connectors), this option allows compensating the propagation delay and the fine alignment of the clock phases. This setting is directly written into the PLL registers and is not permanent. Once the optimal setting has been found, use the PermanentClockOutDelay parameter to store the delay in the flash memory and automatically reload it at every power-up.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: -18888.88888888889
• Max: 18888.88888888889
• Increment: 74.07407407407408
• Set in Run: True
• Unit of Measure: ps

PermanentClockOutDelay

Sets the VolatileClockOutDelay parameter, stores the value into the filesystem and makes it permanent. When read, it returns the value of the delay stored in the filesystem, that may differ from the one currently applied, if volatile.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: -18888.88888888889
• Max: 18888.88888888889
• Increment: 74.07407407407408
• Set in Run: True
• Unit of Measure: ps

Waveform Parameters

MaxRawDataSize

Maximum size that can be returned from a single call to GetData from the Raw endpoint

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Max: 0
• Increment: 1
• Unit of Measure: B

WaveDataSource

In normal mode, the acquired waveform represents a sequence of ADC samples, resulting from the A/D conversion of the analog input. For test purposes, it is possible to replace the ADC data with internal data generators.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• ADC_DATA: Data from the ADC (normal operating mode)
• ADC_TEST_TOGGLE: Toggle between 0x5555 and 0xAAAA (test mode)
• ADC_TEST_RAMP: 16-bit ramp pattern (test mode)
• ADC_TEST_SIN: 8-point sine wave test pattern
• ADC_TEST_PRBS: 16-bit PRBS generated by a 23-bit PRBS pattern generator (test mode)
• Ramp: Data from a ramp generator. It is actually a 16-bit field, where the 6 most significant bits identify the channel and the 10 less significant bits are the samples of a ramp from 0x000 up to 0x3FF (i.e. 0 to 1023). It is so a 10-bit ramp with offset given by "channel*1024". For channel 0, it is a counter from 0 to 1023; for channel 1, it is a counter from 1024 to 2047, and so on
• IPE: Not implemented
• SquareWave: Internally generated programmable square wave

RecordLengthS

The waveform Size (i.e. size of the acquisition window). The actual size of the waveform will be automatically rounded to the closest allowed value. It is possible to get the exact size by reading back the parameter. The record length in time depends on wave resolution.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 16380
• Increment: 4
• Set in Run: True
• Unit of Measure: S

ChPreTriggerS

Number of samples coming before the position of the trigger in the waveform (i.e. size of the pre-trigger window).

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 4095
• Increment: 1
• Set in Run: True
• Unit of Measure: S

Service Parameters

TestPulsePeriod

The Test Pulse is a programmable square wave that can be used as an internal periodic trigger (mainly for test purposes) or to generate a logic test pulse (TTL or NIM) on the TRGOUT and GPIO outputs. This parameter sets the period of the Test Pulse.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 34359738360
• Increment: 8
• Set in Run: True
• Unit of Measure: ns

TestPulseWidth

Width of the Test Pulse (time that the signal stays high = 1).

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 34359738360
• Increment: 8
• Set in Run: True
• Unit of Measure: ns

TestPulseLowLevel

Low level of the Test Pulse expressed in ADC counts

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 65535
• Increment: 1
• Set in Run: True
• Unit of Measure: ADC counts

TestPulseHighLevel

High level of the Test Pulse expressed in ADC counts

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 65535
• Increment: 1
• Set in Run: True
• Unit of Measure: ADC counts

IOlevel

Sets the electrical logic level of the LEMO I/Os (TRGIN, SIN, TRGOUT, GPIO).

Note that TRGIN and SIN are internally terminated to 50 Ohm, while GPIO and TRGOUT require the termination to 50 Ohms at the receiver

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• NIM: NIM logic (0 = 0V, 1 = -0.8V, that is -16mA)
• TTL: Low Voltage TLL logic (0 = 0V, 1 = 3.3V)

TempSensAirIn

Sensor monitoring the temperature of the incoming air flow of the board. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensAirOut

Sensor monitoring the temperature of the outcoming air flow of the board. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensCore

Sensor monitoring the temperature of the FPGA core. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensFirstADC

Sensor monitoring the temperature of the first ADC core. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensLastADC

Sensor monitoring the temperature of the last ADC core. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensHottestADC

Sensor monitoring the temperature of the last ADC core. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC0

Sensor monitoring the temperature of the ADC sensor #0. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC1

Sensor monitoring the temperature of the ADC sensor #1. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC2

Sensor monitoring the temperature of the ADC sensor #2. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC3

Sensor monitoring the temperature of the ADC sensor #3. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC4

Sensor monitoring the temperature of the ADC sensor #4. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC5

Sensor monitoring the temperature of the ADC sensor #5. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC6

Sensor monitoring the temperature of the ADC sensor #6. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensADC7

Sensor monitoring the temperature of the ADC sensor #7. The resolution is 0.1 °C. Not available for digitizer with pcb rev 0.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

TempSensDCDC

Sensor monitoring the temperature of the DC-DC converter. The resolution is 0.1 °C.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: °C

VInSensDCDC

Sensors monitoring the input voltage of the DC-DC converter. The resolution is 0.001 V.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.001
• Set in Run: False
• Unit of Measure: V

VOutSensDCDC

Sensors monitoring the output voltage of the DC-DC converter. The resolution is 0.001 V.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.001
• Set in Run: False
• Unit of Measure: V

IOutSensDCDC

Sensor monitoring the DC-DC converter current. The resolution is 0.001 A.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.001
• Set in Run: False
• Unit of Measure: A

FreqSensCore

Frequency of the DCDC converter. The resolution is 0.1 kHz.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: kHz

DutyCycleSensDCDC

Duty Cycle of the DCDC converter. The resolution is 0.1 percent.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 0.1
• Set in Run: False
• Unit of Measure: %

SpeedSensFan1

Sensor monitoring the fan speed #1 (desktop modules only). The resolution is 1 rpm.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 1
• Set in Run: False
• Unit of Measure: rpm

SpeedSensFan2

Sensor monitoring the fan speed #2 (desktop modules only). The resolution is 1 rpm.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 1
• Set in Run: False
• Unit of Measure: rpm

ErrorFlagMask

All these errors can be combined into a Global Error Flag through a masked OR, programmed by this parameter.

Bit	Description
0	power_fail
1	board_init_fault
2	si5341_unlock
3	si5395_unlock
4	LMK04832_unlock
5	jesd_unlock
6	ddr_pl_bank0_calib_fail
7	ddr_pl_bank1_calib_fail
8	ddr_ps_calib_fail
9	fpga_config_fail
10	bic_error
11	adc_overtemp
12	air_overtemp
13	fpga_overtemp
14	dcdc_overtemp
15	clkin_miss
16	adc_shutdown

Additional information about the error bits is included in the Digitizer User Manual.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING

ErrorFlagDataMask

All these errors can be combined into a Data Error Flag through a masked OR, programmed by this parameter.

Bit	Description
0	power_fail
1	board_init_fault
2	si5341_unlock
3	si5395_unlock
4	LMK04832_unlock
5	jesd_unlock
6	ddr_pl_bank0_calib_fail
7	ddr_pl_bank1_calib_fail
8	ddr_ps_calib_fail
9	fpga_config_fail
10	bic_error
11	adc_overtemp
12	air_overtemp
13	fpga_overtemp
14	dcdc_overtemp
15	clkin_miss
16	adc_shutdown

Additional information about the error bits is included in the Digitizer User Manual.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING

ErrorFlags

32 bit word with error flags.

Bit	Description
0	power_fail
1	board_init_fault
2	si5341_unlock
3	si5395_unlock
4	LMK04832_unlock
5	jesd_unlock
6	ddr_pl_bank0_calib_fail
7	ddr_pl_bank1_calib_fail
8	ddr_ps_calib_fail
9	fpga_config_fail
10	bic_error
11	adc_overtemp
12	air_overtemp
13	fpga_overtemp
14	dcdc_overtemp
15	clkin_miss
16	adc_shutdown

Additional information about the error bits is included in the Digitizer User Manual.

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

BoardReady

Check if there is any error set in ErrorFlags

Options:

• Level: DIG
• Access Mode: READ_ONLY
• Type: STRING

Allowed Values:

• True: ErrorFlags is zero
• False: Otherwise

Individual Trigger Parameters

ITLAMainLogic

Each channel of the digitizer feature a digital bipolar triangular filter discriminator with programmable rise time and threshold able to self-trigger on the input pulses and generate a self-trigger signal. In DPP Mode, the channels acquire independently, so the channel self-trigger is used locally to acquire a waveform. The trigger threshold is then referred to the bipolar triangular filter, and the threshold crossing arms the event selection. The trigger fires at the zero crossing of the time filter signal. The user can see the derivative trace on the signal inspector. It is also possible to combine all the self-triggers of the board, according to a specific trigger logic. There are two independent logic blocks, ITLA and ITLB. Their output can be used separately to feed, for instance, AcqTrigger and TrgOut, or combined in a second level trigger logic to implement more complex trigger schemes. Therefore, the ITLs can either generate the local acquisition trigger, common to all the channels, for the acquisition of the waveform, or propagate the signal outside, through the TRGOUT, thus making it possible to combine triggers of multiple boards in an external trigger logic, that eventually feeds back the TRGIN of the digitizers. Each ITL is made of an input enable mask (64 bits, one per channel), an optional pairing logic that combines the self triggers of two consecutive channels (e.g. paired coincidence) and the main trigger logic that combines the 64 selftriggers with an OR, AND or Majority logic. The output can be linear (no stretching) or reshaped by a programmable gate generator, either re-triggerable or not and finally programmed for polarity (direct or inverted).

Fig 2: Individual Trigger logic scheme

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• OR: ITLOUT = masked OR of channel self-triggers
• AND: ITLOUT = masked AND of channel self-triggers
• Majority: ITLOUT = masked Majority of channel self-triggers

ITLBMainLogic

Each channel of the digitizer feature a digital bipolar triangular filter discriminator with programmable rise time and threshold able to self-trigger on the input pulses and generate a self-trigger signal. In DPP Mode, the channels acquire independently, so the channel self-trigger is used locally to acquire a waveform. The trigger threshold is then referred to the bipolar triangular filter, and the threshold crossing arms the event selection. The trigger fires at the zero crossing of the time filter signal. The user can see the derivative trace on the signal inspector. It is also possible to combine all the self-triggers of the board, according to a specific trigger logic. There are two independent logic blocks, ITLA and ITLB. Their output can be used separately to feed, for instance, AcqTrigger and TrgOut, or combined in a second level trigger logic to implement more complex trigger schemes. Therefore, the ITLs can either generate the local acquisition trigger, common to all the channels, for the acquisition of the waveform, or propagate the signal outside, through the TRGOUT, thus making it possible to combine triggers of multiple boards in an external trigger logic, that eventually feeds back the TRGIN of the digitizers. Each ITL is made of an input enable mask (64 bits, one per channel), an optional pairing logic that combines the self triggers of two consecutive channels (e.g. paired coincidence) and the main trigger logic that combines the 64 selftriggers with an OR, AND or Majority logic. The output can be linear (no stretching) or reshaped by a programmable gate generator, either re-triggerable or not and finally programmed for polarity (direct or inverted).

Fig 3: Individual Trigger logic scheme

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• OR: ITLOUT = masked OR of channel self-triggers
• AND: ITLOUT = masked AND of channel self-triggers
• Majority: ITLOUT = masked Majority of channel self-triggers

ITLAMajorityLev

Defines the majority level of the Main Logic of the ITL A block. The majority output is calculated at every clock cycle, and it becomes TRUE when Nch >= MajLev, where Nch is the number of self-triggers active in that clock cycle and MajLev is the programmed majority level.

Note that when the Pair Logic is used to combine the self triggers two by two (AND/OR), each pair produces two identical signals that will be counted twice in the majority level.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 63
• Increment: 1
• Set in Run: False

ITLBMajorityLev

Defines the majority level of the Main Logic of the ITL B block. The majority output is calculated at every clock cycle, and it becomes TRUE when Nch >= MajLev, where Nch is the number of self-triggers active in that clock cycle and MajLev is the programmed majority level.

Note that when the Pair Logic is used to combine the self triggers two by two (AND/OR), each pair produces two identical signals that will be counted twice in the majority level.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 63
• Increment: 1
• Set in Run: False

ITLAPairLogic

Pairs of channels can be combined with an OR or AND before feeding in the Main trigger Logic. This is typically used in the readout of tubes or scintillator bars, where the two ends are read in coincidence, for instance in position sensitive detectors (the coincidence window will be set by the SelfTriggerWidth parameter). When the AND/OR logic is applied, the two outputs of the Pair Logic blocks are identical.

Note that they are counted twice in the following Majority logic. If the Pair Logic is disabled ("NONE" option), the block is transparent, and the two outputs are just a replica of the inputs.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• OR: Both Pair Logic Outputs = OR of two consecutive self-triggers
• AND: Both Pair Logic Outputs = AND of two consecutive self-triggers
• NONE: Outputs = Inputs

ITLBPairLogic

Pairs of channels can be combined with an OR or AND before feeding in the Main trigger Logic. This is typically used in the readout of tubes or scintillator bars, where the two ends are read in coincidence, for instance in position sensitive detectors (the coincidence window will be set by the SelfTriggerWidth parameter). When the AND/OR logic is applied, the two outputs of the Pair Logic blocks are identical.

Note that they are counted twice in the following Majority logic. If the Pair Logic is disabled ("NONE" option), the block is transparent, and the two outputs are just a replica of the inputs.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• OR: Both Pair Logic Outputs = OR of two consecutive self-triggers
• AND: Both Pair Logic Outputs = AND of two consecutive self-triggers
• NONE: Outputs = Inputs

ITLAPolarity

Polarity of the gate generator output.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Direct: Direct polarity
• Inverted: Inverted polarity

ITLBPolarity

Polarity of the gate generator output.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Direct: Direct polarity
• Inverted: Inverted polarity

ITLAMask

Polarity of the gate generator output.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

ITLBMask

Polarity of the gate generator output.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

ITLConnect

Alternative to ITLAMask, ITLBMask. Determines if the channel partecipate in ITLA or ITLB

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Disabled: The channel is disabled
• ITLA: The channel participates in ITLA logic block
• ITLB: The channel participates in ITLB logic block

ITLAGateWidth

Width of the gate generator at the output of the ITLA block.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 524280
• Increment: 8
• Set in Run: False
• Unit of Measure: ns

ITLBGateWidth

Width of the gate generator at the output of the ITLB block.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 524280
• Increment: 8
• Set in Run: False
• Unit of Measure: ns

LVDS Parameters

LVDSMode

The digitizer is equipped with 16 LVDS I/Os that can be programmed to be inputs or outputs by groups of 4 (quartets), depending on the LVDSDirection parameter. Once the direction has been selected, it is possible to select the functionality of the LVDS lines, individually for each quartet.

Options:

• Level: LVDS
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• SelfTriggers: This option is available only when the LVDS are set as outputs. Each LVDS line can be assigned to a combination of the 64 self-triggers, implemented as a masked OR, where the mask is set by the LVDSTrgMask parameter(16 independent masks, one per LVDS line)
• Sync: _Whatever is the direction of the quartet, the 4 lines are rigidly assigned to specific acquisition signals:

0 = Run 1 = Trigger 2 = Busy 3= Veto It is possible to implement a daisy chain distribution of these signals using one quartet as input and another one as output_

* IORegister: The LVDS lines of the quartet are statically controlled by the LVDSIOReg parameter. Use the SetValue function to set the relevant LVDS lines when programmed as output. Use GetValue to read the status of the LVDS lines when programmed as inputs.

• User: User custom.

LVDSDirection

Assigns the direction to a quartet of LVDS I/Os.

Options:

• Level: LVDS
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Input: The LVDS lines of the relevant quartet are used as input. The relevant LED on the front panel is OFF.
• Output: The LVDS lines of the relevant quartet are used as output. The relevant LED on the front panel lights-up.

LVDSIOReg

Set the status of the LVDS I/O for the quartets when they are programmed to be output and Mode = IORegister. This parameter reads out the status of the quartets in the case the LVDS I/O are programmed as inputs (possibly externally driven).

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

LVDSTrgMask

Each LVDS line can be assigned to a combination of the 64 self-triggers, implemented as a masked OR, where the mask is set by this parameter. There are 16 independent masks, one per LVDS line. Note that the trigger mask assignment does not imply the LVDS direction and mode settings. It is therefore necessary to set the Direction = Output and Mode = SelfTriggers to use the Self-Trigger propagation to the LVDS I/Os.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Front Panel LEMO DAC Parameters

DACoutMode

Selects the signal type to be sent in output on the front panel DAC connector.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: True

Allowed Values:

• Static: DAC output stays at a fixed level, given by the DACoutStaticLevel parameter
• Ramp: The DAC output is driven by a 14-bit counter
• Sin5MHz: The DAC output is a sine wave at 5 MHz with fixed amplitude
• Square: Square wave with period and with set by TestPulsePeriod and TestPulseWidth and amplitude between TestPulseLoweLevel and TestPulseHighLevel.
• IPE: Not implemented
• ChInput: The DAC reproduces the input signal received by one input channel, selected by the DACoutChSelect parameter
• MemOccupancy: Level of the memory occupancy (not yet implemented)
• ChSum: The DAC reproduces the "analog" sum of all the digitizer inputs (not yet implemented)
• OverThrSum: The DAC output is proportional to the number of channels that are currently above the threshold

DACoutStaticLevel

When DACoutMode = Static, this parameter sets the 14-bit level of the DAC static output.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 16383
• Increment: 1
• Set in Run: True

DACoutChSelect

When DACoutMode = ChInput, the DAC reproduces the input signal of the channel selected by this parameter.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 63
• Increment: 1
• Set in Run: True

Input Signal Conditioning Parameters

InputDelay

Set input delay. The value is set at groups of 4 channels.

Options:

• Level: GROUP
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 4095
• Increment: 1
• Set in Run: False
• Unit of Measure: S

EnOffsetCalibration

The input DC offset that determines the position of the signal baseline (zero Volts) is controlled by individual channel DACs. Due to the tolerance of the components, there is some spread in the offset setting that is compensated by the offset calibration. This is normally enabled and automatically applied in the firmware of the board. The calibration can be disabled, mainly when a new calibration must be calculated.

Options:

• Level: DIG
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• True: DC offset calibration is applied (default)
• False: DC offset calibration is not applied

ChEnable

Enable the channels for the acquisition, according to the Index. When the channel is disabled, it does not give any data and its self-trigger is off.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• True: The channel is enabled for the acquisition
• False: The channel is disabled for the acquisition

ChStatus

Gets a 32-bit word representing the status of the channel.

Bit	Description
0	Error in setting the threshold which generates the over-threshold signal and the consequent trigger, if enabled.
1	Not used
23:2	Not used
31:24	Channel index (actually coded over 6 bits, so bit 31 and 30 are always 0)

Options:

• Level: CH
• Access Mode: READ_ONLY
• Type: STRING

DCOffset

A constant DC offset (controlled by a 16-bit DAC) is added to the analog input, individually for each channel, to adjust the position of the signal baseline (that is the "zero volt" of the analog input) within the dynamic range of the ADC. Because of the tolerance of the components, it is necessary to calibrate the offset DAC. The calibration is done by factory testing and normally it is not necessary to recalibrate the digitizer. It is however possible to perform a new calibration. The calibration parameters are stored in the flash memory of the board and loaded at power on. They are automatically applied by the internal logic every time the DCoffset parameter is written or read. DCoffset is expressed as a NUMBER number, in percent of the full-scale. When the DCoffset is 0, the baseline of the input signal is at 0 ADC counts. When the DCoffset is 100, the baseline of the input signal is at 2^NBIT-1 ADC counts.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 100
• Increment: 0.001
• Set in Run: True
• Unit of Measure: %

SignalOffset

Offset of the input signal.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: -1000000
• Max: 1000000
• Increment: 1
• Set in Run: True
• Unit of Measure: uV

GainFactor

Reads the gain ADC calibration value stored in the internal flash. This value can be used by the user in its own DAQ software to calibrate the ADC and provide the signal amplitude value in milliVolts (mV) units.

Options:

• Level: CH
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 1e-06
• Set in Run: True

ADCToVolts

Returns the factor to convert ADC counts to volts.

Options:

• Level: CH
• Access Mode: READ_ONLY
• Type: NUMBER
• Min: 0
• Increment: 1e-09
• Set in Run: True
• Unit of Measure: V

TriggerThr

Each channel of the digitizer has a digital leading-edge discriminator with programmable threshold able to self-trigger on the input pulses and generate a self-trigger signal (or an overthreshold signal) feeding the internal trigger logics or digitizer outputs. This parameter sets the trigger threshold. Typically, the value is relative to the baseline of the signal and the threshold is a 17-bit signed NUMBER number; in this case, the threshold automatically follows the baseline when the DCoffset parameter changes. Sometimes, it is preferable to set an absolute value for the threshold, referred to the ADC range. In this case, the threshold is unsigned NUMBER number.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 65535
• Increment: 1
• Set in Run: True
• Unit of Measure: ADC counts

PulsePolarity

Allows to set the polarity of the input pulse.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Positive: Positive polarity
• Negative: Negative polarity

VGAGain

Sets the gain of the Variable Gain Amplifiers (VGA) in steps of 0.5 dB. The gain is set commonly to a group of 16 channels depending on the Index: Index[0] means CH0-CH15.

Options:

• Level: VGA
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 40
• Increment: 0.5
• Set in Run: True
• Unit of Measure: dB

DPP Algorithm Parameters

ZLEChSupprThr

The ZLE algorithm further checks whether the ZLE suppression threshold (ZLESupprThreshold) is crossed and saves the overthreshold samples (under threshold in case of negative polarity), which are referred as "good" samples. In addition, also a programmable number of samples can be acquired before and after the over/under threshold (ChLookBackSamples and ChLookForwardSamples respectively). "Skipped" samples are discarded; only a word reporting the number of skipped samples is present in the final data. This parameter allows to set the ZLE data suppression threshold. Similarly to the TriggerThr, this threshold is relative to the baseline whose value is determined by the DCOffset.

The figure below shows the parameters of the ZLE algorithm. The signal recording starts ChLookBackSamples samples before the ZLE threshold crossing (LBW in the picture) and stops ChLookForwardSamples samples after the crossing in the opposite direction (LFW in the picture). The recorded regions define the ROI (region of interest) of the algorithm. Outside the ROI the algorithm reports the number of skipped samples.

Fig 4: ZLE algorithm description.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 65535
• Increment: 1
• Set in Run: True
• Unit of Measure: ADC counts

ChLookBackSamples

This parameter allows to set the ZLE look-back samples.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 1023
• Increment: 1
• Set in Run: True
• Unit of Measure: S

ChLookForwardSamples

This parameter allows to set the ZLE look-forward samples.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 1023
• Increment: 1
• Set in Run: True
• Unit of Measure: S

EnZLESuppr

When this bit is set, no ZLE data reduction is applied.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• True: ZLE Data reduction is enabled.
• False: ZLE Data reduction is disabled.

DefaultValueSource

Selection of the default sample value in the payload (baseline or register).

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: STRING
• Set in Run: False

Allowed Values:

• Baseline: Default sample value is Baseline.
• Register: Default sample value is the value.

DefaultValueRegister

ZLE default sample value register.

Options:

• Level: CH
• Access Mode: READ_WRITE
• Type: NUMBER
• Min: 0
• Max: 65535
• Increment: 1
• Set in Run: True
• Unit of Measure: ADC counts