Digital Pulse Processing (DPP)

Firmware

Digital Pulse Processing (DPP)

Digital Pulse Processing (DPP) Models

DPP-DAW

DPP-DAW

  • Independent channel self-trigger

  • Automatic adjustment of the acquisition window length to match the actual input pulse duration

  • User defined minimum record length and pre-trigger for a complete event reconstruction

  • Continuous signal baseline calculation for baseline drift compensation

  • Programmable input delay to compensate for veto generation latency

  • Channel Trigger Time Tag for event correlation
DPP-PHA

DPP-PHA

  • Digital solution equivalent to Shaping Amplifier and Peak Sensing ADC

  • Trapezoidal Filter for Pulse Height Analysis

  • Supported by:

    • CAEN CoMPASS Software

    • MC2Analyzer Software

    • NSCLDAQ Software (725-730 series)

  • Energy spectra measurements

  • Self-Trigger using RC-CR2 digital algorithm

  • Online baseline restoration and ballistic effect correction

  • Programmable input offset, trigger and energy filter parameters

  • Online correction of pile-up for high counting rate measurements

  • On-line coincidences/anti-coincidence acquisition mode among channels

  • Timing information (pulse timestamps and/or rise/fall time)

  • Free downloadable firmware trial version
DPP-PSD

DPP-PSD

  • Digital solution equivalent to Dual Gate QDC + Discriminator + Gate Generator

  • Implemented in the digitizer families:

    • 720 (12-bit @ 250 MS/s)

    • 725 (14-bit @ 250 MS/s)

    • 730 (14-bit @ 500 MS/s)

    • 751 (10-bit @ 1 GS/s)

    • 2740 (16-bit @ 125 MS/s)

    • 2745 (16 bit @ 125 MS/s)

    • DT5790 Digital Pulse Analyzer (12 bit @ 250 MS/s)

  • Fully supported by the CoMPASS software

  • NSCLDAQ Supported

  • Double charge integration for Pulse Shape Discrimination

    • Programmable width and position of the two gates

  • Single gate integration for energy spectra calculation

  • Self-Gating (no discriminator) with digital noise filtering

    • No delay line is needed to fit the position of the pulse inside the gate

  • Automatic baseline subtraction (pedestal)

  • Digital Constant Fraction Discrimination for fine time stamp interpolation (pico-second intrinsic resolution)

    • Timing information (pulse time-stamps)

  • No conversion time to reduce the dead-time of the acquisition

  • On-line coincidences/anti-coincidences acquisition mode among channels

  • Free downloadable firmware trial version
DPP-QDC

DPP-QDC

  • Digital solution equivalent to Single Gate QDC + Discriminator + Gate Generator

  • Runs only on x740D models

  • Single gate integration for Energy spectra calculation

  • Self-Gating (no discriminator) with digital noise filtering

  • No delay line is needed to fit the position of the pulse inside the gate

  • Independent 32 (Desktop, NIM) – 64 (VME) channel self-trigger

  • Trigger adjustment for single channel

  • Programmable gate width and position for single channel

  • Automatic Baseline subtraction (pedestal)

  • Dead-timeless acquisition (no conversion time)

  • Provides also timing information (pulse time stamps)

  • Free downloadable firmware trial version

  • Fully supported by the CoMPASS multiparametric acquisition software

  • Demo software to handle 740 digitizer family running DPP-QDC firmware
DPP-SUP

DPP-SUP

  • DPP-SUP License covers different CAEN DPP firmware on a single digitizer

  • The license is available for 725, 730, and 2740-45 digitizer series

  • DPP Algorithms licensed:

    • Pulse Height Analysis (DPP-PHA)

    • Pulse Shape Discrimination (DPP-PSD)

    • Zero Length Encoding (DPP-ZLEplus)

    • Dynamic Acquisition Window (DPP-DAW)

  • The license automatically applies also to incoming new DPP algorithms
DPP-ZLEPLUS

DPP-ZLEPLUS

  • Enhanced Zero Suppression of input signals

  • Input signal baseline calculation

  • ZLE Threshold (two values for 751 series)

  • Programmable Look Back and Look Forward windows.

  • Acquisition window synchronized with an external trigger or an internal global trigger (725-730 only)

  • Provides also timing information (trigger time stamps)

  • Compliant with:

    • 725, 730, 740, 745 and 751 digitizer families

  • Source files and Visual Studio project available for free
FW1495SC

FW1495SC

  • Up to 128 Channel Latching Scaler

  • 250 MHz maximum counting frequency

  • 32 bit channel depth

  • Multichannel scaler operation with programmable dwell time from 1 µsec to ~ 1 hour

  • 4 k x 32 bit multievent buffer memory

  • Trigger time tag

  • VME Block Transfer support

  • Free Trial version download
FW2495SC

FW2495SC

  • Up to 160 Channel Latching Scaler

  • Up to 200 MHz of counting frequency

  • 64-bit channel depth

  • Multichannel scaler operation with programmable dwell time from 1 µs to 4000 s

  • 4 k x 32 bits multievent buffer memory

  • 64-bit Trigger time tag

  • VME Block Transfer support

  • Event payload legacy option for V1495 compliance

  • Free Trial version download

  • Windows compliant demo program with C source files and VS project for developers